A 5.5mW ADPLL-Based Receiver with HybridLoop Interference Rejection for BLE Application in 65nm CMOS

📋 论文概要

本文提出了一种基于ADPLL的接收机，采用混合环路干扰抑制技术，在65nm CMOS工艺下实现5.5mW功耗，解决了传统PLL接收机邻道干扰抑制不足的问题，满足BLE应用需求。

💡 主要创新点

• 1. 使用全数字锁相环（ADPLL）架构实现低功耗接收机。
• 2. 提出混合环路（HybridLoop）干扰抑制方法，在不引入高阶滤波器的前提下提升邻道干扰抑制能力，避免闭环稳定性恶化。

🏷 关键词

📄 原文摘要

(BLE) have been developed for minimizing the RX power consumption. A PLL-based RX architecture [1] is very attractive to improve the energy efficiency. While the single-channel configuration without multi-bit ADC realizes under 3mW power consumption and over -90dBm sensitivity, the 2nd and 3rd Adjacent Channel Interference Rejections (ACRs) do not meet the BLE requirements. Although the ACR can be improved by inserting high-order LPFs into the regeneration loop, it critically degrades the closed-loop stability. The Sliding IF (SIF) architecture is an alternative approach to overcome the ACR issue with high-energy efficiency. The reported receivers in [2,3] succeed in achieving over 20dB ACR, however, the SIF still has a problem of low out-of-band blocker tolerance because of unwanted

👥 作者与机构

Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo,

Takashi Tokairin, Masanori Furuta, Tetsuro Itakura Toshiba, Kawasaki, Japan Various Ultra-Low-Power (ULP) RX architectures [1-4] for BluetoothTM Low Energy