Mb/mm2 1R1W 8T SRAM Arrays Operating down to 560mV Utilizing Small-Signal Sensing with Charge-Shared Bitline and Asymmetric Sense Amplifier in 14nm FinFET CMOS Technology

📋 论文概要

本文提出了一种工作在560mV低电压下的1R1W 8T SRAM阵列，利用小信号传感和电荷共享位线技术解决了传统双端口SRAM的读干扰和写干扰问题，实现了高密度（Mb/mm2）存储。

💡 主要创新点

• 采用小信号传感与电荷共享位线技术，使SRAM能在低至560mV的电压下工作
• 改进的1R1W 8T去耦双端口单元设计，消除了读干扰并支持同时读写操作
• 非交错阵列布局防止伪读干扰，提高了读写稳定性

🏷 关键词

📄 原文摘要

which use multiport memories to improve performance by enabling multiple simultaneous operations in the same memory bank. Conventional 2-read/write 8T dual-port SRAMs (2RW) suffer from read and write disturb issues when both wordlines in one row are activated at the same time. 1-read, 1-write 8T decoupled dual port cells (1R1W) eliminate read disturb by preventing charge-sharing with internal storage nodes while the read wordline (RDWL) is activated. Dummy-read disturb can also be prevented in 1R1W arrays by using a non-interleaved design. The single-ended read port in 1R1W cells typically leads to the use of large signal sensing. This in turn necessitates the adoption of a hierarchical bitline scheme with short local bitlines (LBLs), which minimize the capacitive load discharged

👥 作者与机构

John Keane, Jaydeep Kulkarni, Kyung-Hoae Koo,

Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang Intel, Hillsboro, OR System-on-Chip (SoC) designs contain a variety of IP blocks