A Digital PLL with Feedforward Multi-Tone Spur Cancelation Loop Achieving <-73dBc Fractional Spur and <-110dBc Reference Spur in 65nm CMOS

📋 论文概要

本文提出了一种带有前馈多音调杂散消除环路的分数-N数字PLL，有效降低了分数杂散和参考杂散，实现了<-73dBc的分数杂散和<-110dBc的参考杂散，解决了PLL中杂散干扰问题。

💡 主要创新点

• 提出前馈多音调杂散消除环路，可同时抑制多个频率的杂散。
• 在分数-N数字PLL架构中实现，无需额外模拟电路，节省功耗和面积。

🏷 关键词

📄 原文摘要

A low-spur PLL is desirable for many applications since it avoides mixing unwanted blocker signals, prevents emission mask violations or minimizes jitter in the clock source. Internal spurs result from the nature of PLL operation and include reference spurs and fractional spurs when the PLL is operated in fractional-N mode. External spurs are caused by nearby disturbances, such as coupling from other clock domains in an SoC design. To achieve ultra-low spur levels, this work proposes a feedforward multi-tone spur cancellation loop for a fractional-N digital PLL architecture. The proposed scheme aims to cancel: a) fractional spurs caused by finite time-to-digital converter (TDC) quantization steps and its DNL when operated in fractional-N mode; b) external spurious tones that are in a harmonic relationship, and c) independent series of spurious tones that are not in a mutually harmonic relationship by cascading cancellation loops. A

👥 作者与机构

Cheng-Ru Ho, Mike Shuo-Wei Chen

University of Southern California, Los Angeles, CA