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ISSCC 2016Session 15 · OVERSAMPLING DATA CONVERTERSData Converters

A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM

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📋 论文概要

该论文提出了一种1V供电、77dB动态范围、72dB SNDR、10MHz带宽的2-1 MASH连续时间ΔΣ调制器。通过采用MASH结构实现高阶噪声整形,并利用简单放大器(如单级或反相器型)降低功耗,同时结合有源-无源架构减少放大器数量。

💡 主要创新点

核心指标
72dB SNDR @ 10MHz带宽
重要性
发表年份
ISSCC 2016

🏷 关键词

MASH连续时间ΔΣ调制器低功耗有源-无源架构

📄 原文摘要

DEE, FCT, Universidade NOVA de Lisboa, Caparica, Portugal, CTS-UNINOVA, Caparica, Portugal 1 2 ΔΣM performance can be improved by using MASH or SMASH structures to obtain higher-order noise shaping [1]. They have better stability than single-loop structures. The power dissipation of ΔΣMs can be reduced by using simpler amplifiers such as single-stage or inverter-based amplifiers [2]. Selecting a passive or active-passive ΔΣM architecture, where the processing gain of comparator is used in the feedback loop of the ΔΣM’s filter [3], allows a reduction in the number of amplifiers and their gain. This solution is very appealing for deepnanometer CMOS technologies, because a comparator can achieve large gain through positive feedback, which improves with faster transistors. This paper presents a passive-active CT 2-1 MASH ΔΣM using RC integrators, low-gain stages (~20dB) and simplified digital cancellation logic (DCL). The ΔΣM, clocked

👥 作者与机构

Blazej Nowacki1,2, Nuno Paulino1,2, Joao Goes1,2

分类:Data Converters · 年份:ISSCC 2016