A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB Built-In Supply Noise Rejection and Self-Bandwidth Control in 14nm CMOS

📋 论文概要

该论文提出了一种用于SoC的锁相环（PLL），在0.15至5GHz频率范围内功耗仅为0.17至3.5mW，并具备15dB内置电源噪声抑制和自带宽控制功能。该PLL采用模块化设计，可作为本地时钟源或时钟生成中枢的一部分，有效解决了SoC中多PLL系统的低功耗和高电源噪声抑制需求。

💡 主要创新点

• 提出了一种具有15dB内置电源噪声抑制的环形振荡器数字控制振荡器（DCO），显著降低了电源噪声对PLL性能的影响。
• 实现了自带宽控制功能，使PLL能在宽频率范围内自动调整带宽，优化了功耗与抖动性能的权衡。
• 采用模块化设计，支持作为本地时钟源或时钟生成中枢，提高了SoC时钟系统的灵活性和可扩展性。

🏷 关键词

📄 原文摘要

architectures can employ more than 20 PLLs [1]. To address SoC clocking needs with an ever reducing power budget, a deep sub-mW to low-mW PLL having a FoM between -226dB and -234dB from 0.8GHz to 5GHz is presented. The PLL features a modular implementation and therefore could be used as the local clock source or as part of a clock-generation hub. The hub provides reference clocks to subsystems from a single platform crystal oscillator through a combination of divisions and distributions. Minimizing the supply sensitivity of the ring oscillator-based digital or voltage control oscillators (DCOs or VCOs), and thus the PLL deterministic jitter (Dj), often leads to adopting a low-dropout (LDO) voltage regulator. Effective Dj reduction typically requires >30dB power-supply rejection ratio across a frequency

👥 作者与机构

Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan,

Khoa Minh Nguyen, Qi Wang, Amr Elshazly, Nasser Kurd Intel, Hillsboro, OR With recent advancements in SoC integration, modern SoC