A 1.2V 20nm 307GB/s HBM DRAM with At-Speed Wafer-Level I/O Test Scheme and Adaptive Refresh Considering Temperature Distribution

📋 论文概要

该论文提出了一款1.2V 20nm工艺的HBM DRAM，实现了307GB/s的高带宽，并引入了晶圆级高速I/O测试方案和考虑温度分布的自适应刷新技术，以满足高性能计算和图形应用对更高带宽DRAM的需求。

💡 主要创新点

• 提出了晶圆级高速I/O测试方案，能够在晶圆阶段进行高速测试，提高测试效率和良率。
• 设计了考虑温度分布的自适应刷新技术，根据芯片内温度差异动态调整刷新间隔，以降低功耗或增强数据保持可靠性。

🏷 关键词

📄 原文摘要

Seong-Young Seo, Min-Sang Park, Dong-Hak Shin, Won-Chang Jung, Sang-Hoon Shin, Je-Min Ryu, Hye-Seung Yu, Jae-Hun Jung, Kyung-Woo Nam, Seouk-Kyu Choi, Jae-Wook Lee, Uksong Kang, Young-Soo Sohn, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Gyo-Young Jin Samsung Electronics, Hwaseong, Korea Demand for higher bandwidth DRAM continues to increase, especially in highperformance computing and graphics applications. However, conventional DRAM devices such as DDR4 DIMM and GDDR5 cannot satisfy these needs since they are bandwidth limited to less than 30GB/s. Also, if multiple GDDR DRAMs are used simultaneously for higher bandwidth, then high power consumption and routing congestion on PCBs become a big concern. In order to overcome these limitations, the high-bandwidth memory (HBM) DRAM was recently introduced[1]. HBM-DRAM uses TSV and interposer technologies enabling multiple chip stacks and wide I/Os between the processor and memory: providing

👥 作者与机构

Kyomin Sohn, Won-Joo Yun, Reum Oh, Chi-Sung Oh,