A 4GS/s Time-Interleaved RF ADC in 65nm CMOS with 4GHz Input Bandwidth

📋 论文概要

该论文提出了一款65nm CMOS工艺下、采样率高达4GS/s、输入带宽达4GHz的时间交织射频ADC，实现了对无线通信频段的直接采样，无需下变频。解决了高速ADC在射频直接采样应用中的带宽和频谱纯度问题。

💡 主要创新点

• 采用时间交织架构实现4GS/s的超高采样率，同时保持4GHz的宽输入带宽。
• 在65nm CMOS工艺下实现了射频直接采样，避免了传统下变频架构的复杂性和功耗。

🏷 关键词

📄 原文摘要

Phillip Elliott2, Bill Foley1, Roy Mason2, Vikas Singh3, Xuejin Wang2 Maxim Integrated Products, North Chelmsford, MA, Maxim Integrated Products, Fort Collins, CO, 3 Maxim Integrated Products, San Jose, CA 1 2 The performance and power consumption of high-speed ADCs has advanced such that some receiver architectures can directly sample the input without downconversion. This work looks to extend the applicability of such high-speed ADCs by digitizing wireless communications bands up to 4GHz with a high level of spectral purity. Fabricated in foundry 65nm CMOS and operating up to 4GS/s with power consumption of 2.2W, the reported ADC achieves noise performance of over 60dBFS and linearity performance of 64dBc at 1.842GHz input frequency. At 3.8GHz input frequency, SNR is dominated by aperture jitter of 50fs and twotone IMD3 is >60dBFS. Any interleaved converter with stringent spectral requirements requires correction

👥 作者与机构

Matt Straayer1, Jim Bales2, Dwight Birdsall2, Denis Daly1,