A 0.2-to-1.45GHz Subsampling Fractional-N AllDigital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection

📋 论文概要

该论文提出了一种0.2-1.45GHz的亚采样分数分频全数字乘法延迟锁定环(MDLL)，通过零偏移孔径鉴相器实现杂散抑制，解决了传统MDLL在分数倍频时杂散性能差的问题。

💡 主要创新点

• 提出了亚采样分数分频全数字MDLL架构，实现宽带频率合成
• 采用零偏移孔径鉴相器进行杂散对消，改善频谱纯度
• 全数字实现，具备紧凑面积、良好可扩展性和低功耗优势

🏷 关键词

📄 原文摘要

Multiplying delay-locked loops (MDLLs) are gaining popularity due to their superior noise performance over conventional phase-locked loops (PLLs) [1,2]. Recent designs are trending towards an all-digital implementation that provides advantages such as compact area, good scalability and low power compared to traditional analog implementations. Achieving fractional frequency multiplication is, however, not very straightforward in MDLLs as the digitally controlled oscillator’s (DCO’s) edge is periodically replaced by a clean reference edge. Recently, a fractional-N MDLL was proposed in [1], where the reference edges are realigned using a digital-to-time converter (DTC). One major drawback of MDLL-based frequency synthesis is that the reference spur is generated at the output spectrum due to the timing mismatch between the phase detection path and reference injection path. One of the contributors to this timing mismatch in

👥 作者与机构

Somnath Kundu1, Bongjin Kim2, Chris H. Kim1

University of Minnesota, Minneapolis, MN, 2Rambus, Sunnyvale, CA