an all-digital PLL (ADPLL). In such studies, a key topic relates to the resolution and linearity of the TDC. Power-hungry techniques, such as a Vernier delay line (VDL) and a time amplifier (TA) [1,2], have been proposed to improve time resolution. Recently, a digital-to-time converter (DTC) has been employed to enable power reductions of the VDL and TA-based TDCs by minimizing the number of VDLs and TAs [3,4]. However, the nonlinearity of the DTC remains a problem, since it is much larger than the time resolution of the TDCs and becomes a significant source of fractional spur in the ADPLL. In [3], the effect of the nonlinearity is decreased by utilizing a dithering technique at the expense of a long calibration time (>100ms). The DTC requires inherently more calibration
Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni,
Masanori Furuta, Tetsuro Itakura Toshiba, Kawasaki, Japan Several research studies have considered replacing traditional analog PLLs with