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该论文提出了一种采用帧脉冲宽度调制（FPWM）方案的20Gb/s串行链路收发器，旨在克服传统多电平调制方案在高速有线链路中面临的信噪比降低和线性度要求更严格的问题。通过在40nm CMOS工艺中实现，该收发器提高了频谱效率并降低了码间干扰。
interference (ISI), which necessitates the enhancement of spectral efficiency. Recently, various modulation schemes including pulse amplitude modulation (PAM) [1], pulsewidth modulation (PWM) [2], permutation modulation (PM) [3] and duo-binary signaling [4] have been investigated in high-speed wireline links to increase spectral efficiency. However, multi-level signaling schemes suffer from SNR reduction and tighter linearity requirements when compared to conventional NRZ signaling. In this work, a 20Gb/s serial link transceiver employing a framedpulsewidth modulation (FPWM) scheme that overcomes the SNR degradation without linearity requirement is presented. The FPWM scheme encodes data at the location and the width of pulses in a frame spanning multiple UIs while
Sejun Jeon1, Woohyun Kwon1, Taehun Yoon2, Jong-Hyeok Yoon1,
Kyeongha Kwon1, Jaehyeok Yang1, Hyeon-Min Bae1 KAIST, Daeoen, Korea 2 Samsung Electronics, Hwaseong, Korea 1 Expanding signal bandwidths in high-speed links is increasing intersymbol