ISSCC 2018 — ISSCC 知识库

ISSCC 2018 Session 1 Plenary

Semiconductor Innovation: Is the party over, or just getting started?

Vincent Roche, President and CEO

Semiconductor Innovation Trends: The hardware paradigm underpinning the Information and Communications Technology (ICT) industry has experienced three major shifts over the past 60 years - the mainframe era, the personal

Analog Devices, Norwood, MA

ISSCC 2018 Session 1 Plenary

Brain-Inspired Technologies: Towards Chips that Think?

Barbara De Salvo, Chief Scientist and Scientific Director

Abstract The advent of the Internet-of-Things has introduced a new paradigm that supports a decentralized and hierarchical communication architecture, where a great deal of analytics processing occurs at the edge and at

CEA-Leti, Université Grenoble Alpes, France

ISSCC 2018 Session 1 Plenary

Future Mobility- Enhanced Society Enabled by Semiconductor Technology

Yukihiro Kato, Senior Executive Director

1. Introduction The automotive industry is in the midst of a once-in-a-century transformation. The industry began adopting semiconductors in the 1960s, starting with rectifier diodes for alternators. Then, the spread of

DENSO, Aichi, Japan

ISSCC 2018 Session 1 Plenary

50 years of Computer Architecture: From the Mainframe CPU to the Domain-Specific TPU and the Open RISC-V Instruction Set

David Patterson, Google and UC Berkeley, 1.

Each had its own unique instructionset architecture (ISA); I/O system; system software (assemblers, compilers, libraries); and market niches (business, scientific, real time). IBM engineers bet that they could invent a s

Our Story Begins in the Early 1960s IBM had four incompatible computer

ISSCC 2018 Session 10 Sensors

Chopped Rate-to-Digital FM Gyroscope with 40ppm Scale Factor Accuracy and 1.2dph Bias

Burak Eminoglu, Bernhard E. Boser

Present implementations of MEMS gyroscopes measure rate indirectly by first converting it to a displacement [1,2]. In this case, the scale factor is a complex function of the transducer and readout circuits. Changes of a

University of California, Berkeley, Berkeley, CA

ISSCC 2018 Session 10 Sensors

Personal Inertial Navigation System Employing MEMS Wearable Ground Reaction Sensor Array and Interface ASIC Achieving a Position Accuracy of 5.5m Over 3km Walking Distance Without GPS

Qingbo Guo1, William Deng2, Ozkan Bebek3, Cenk Cavusoglu4,

Cleveland, OH 1 2 An accurate personal inertial navigation system under GPS-denied environment is highly critical for demanding applications such as firefighting, rescue missions, and military operations. Location-aware

Carlos Mastrangelo1, Darrin Young1 University of Utah, Salt Lake City,

ISSCC 2018 Session 10 Sensors

Multi-Way Interactive Capacitive Touch System with Palm Rejection of Active Stylus for 86" Touch Screen Panels

Jae-Sung An1, Sang-Hyun Han2, Kyeong-Bin Park1, Ju Eon Kim3,

Jae-Hun Ye4, Seung-Hwan Lee1, Ji-Yong Jeong1, Jung Soo Kim1, Kwang-Hyun Baek3, Ki-Seok Chung1, Seong-Kwan Hong1, Oh-Kyong Kwon1 Hanyang University, Seoul, Korea; 2Leading UI, Anyang, Korea Chung-Ang University, Seoul, Ko

ISSCC 2018 Session 10 Sensors

A Noise-Immune Stylus Analog Front-End Using Adjustable Frequency Modulation and LinearInterpolating Data Reconstruction for Both Electrically Coupled Resonance and Active Styluses

Kyung-Hoon Lee1, Sang-Pil Nam1, Jung-Ho Lee1, Michael Choi1,

Hyung-Jong Ko1, San-Ho Byun1, Jin-Chul Lee1, Yong-Hoon Lee1, Yeong-Cheol Rhee1, Yoon-Kyung Choi1, Byung-Hoon Kang2, Chang-Byung Park2, Sungsoo Park2, Taesung Kim2 Samsung Electronics, Hwaseong, Korea Samsung Electronics,

ISSCC 2018 Session 10 Sensors

A 0.91mW/Element Pitch-Matched Front-End ASIC with Integrated Subarray Beamforming ADC for Miniature 3D Ultrasound Probes

Chao Chen1, Zhao Chen1, Deep Bera2, Emile Noothout1, Zu-Yao Chang1,

Mingliang Tan1, Hendrik J. Vos1,2, Johan G. Bosch2, Martin D. Verweij1,2, Nico de Jong1,2, Michiel A. P. Pertijs1 Delft University of Technology, Delft, The Netherlands Erasmus MC, Rotterdam, The Netherlands 1 2 Data acq

ISSCC 2018 Session 10 Sensors

Single-Chip Reduced-Wire Active Catheter System with Programmable Transmit Beamforming and Receive Time-Division Multiplexing for Intracardiac Echocardiography

Gwangrok Jung1, M. Wasequr Rashid1, Thomas M. Carpenter2,

Coskun Tekes1, David M. J. Cowell2, Steven Freear2, F. Levent Degertekin1, Maysam Ghovanloo1 Georgia Institute of Technology, Atlanta, GA University of Leeds, Leeds, United Kingdom 1 2 Intracardiac echocardiography (ICE)

ISSCC 2018 Session 10 AI / ML

A 0.3ppm Dual-Resonance Transformer-Based DriftCancelling Reference-Free Magnetic Sensor for Biosensing Applications

Constantine Sideris, Parham Porsandeh Khial, Bill Ling, Ali Hajimiri

Cost-efficient, point-of-use diagnostics are critical for early disease detection. Traditionally, the majority of lab-based analysis equipment utilizes fluorescent markers for biodetection assays. However, magnetic-based

California Institute of Technology, Pasadena, CA

ISSCC 2018 Session 10 Sensors

A 100mK-NETD 100ms-Startup-Time 80×60 MicroBolometer CMOS Thermal Imager Integrated with a 0.234mm2 1.89μVrms Noise 12b Biasing DAC

Ki-Duk Kim1, Seunghyun Park1, Kye-Seok Yoon1, Gyeong-Gu Kang1, Hyun-Ki Han1,

Ji-Su Choi1, Min-Woo Ko1, Jeong-hyun Cho1, Sangjin Lim1, Hyung-Min Lee2, Hyun-Sik Kim3, Kwyro Lee1, Gyu-Hyeong Cho1 KAIST, Daejeon, Korea; 2Korea University, Seoul, Korea Dankook University, Cheonan, Korea 1 3 A micro-bo

ISSCC 2018 Session 11 Memory

A 23.6Mb/mm2 SRAM in 10nm FinFET Technology with Pulsed PMOS TVC and Stepped-WL for Low-Voltage Applications

Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer,

accompanied by a sustained growth of battery-powered mobile devices, continues to drive the importance of energy and area efficient CPU and SoC designs. Low-voltage operation remains one of the primary approaches for act

Xiaofei Wang, Eric Karl Intel, Hillsboro, OR The emergence of cloud co

ISSCC 2018 Session 11 Memory

A 7nm FinFET SRAM Using EUV Lithography with Dual Write-Driver-Assist Circuitry for Low-Voltage Applications

Taejoong Song, Jonghoon Jung, Woojin Rim, Hoonki Kim, Yongho Kim,

Changnam Park, Jeongho Do, Sunghyun Park, Sungwee Cho, Hyuntaek Jung, Bongjae Kwon, Hyun-Su Choi, JaeSeung Choi, Jong Shik Yoon Samsung Electronics, Hwaseong, Korea SRAM plays an integral role in the power, performance,

ISSCC 2018 Session 11 Memory

A 5GHz 7nm L1 Cache Memory Compiler for High-Speed Computing and Mobile Applications

Michael Clinton1, Rajinder Singh1, Marty Tsai1, Shayan Zhang1,

will typically determine the maximum frequency (fMAX) of the processor core. Companies that mass produce high-performance microprocessors commonly have the L1 cache consist of fully-custom macros: to ensure that the perf

Bryan Sheffield1, Jonathan Chang2 TSMC, Austin, TX TSMC, Hsinchu, Taiw

ISSCC 2018 Session 12 Memory

A 16Gb 18Gb/s/pin GDDR6 DRAM with Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, Yoon-Joo Eom,

Young-Sik Kim, Min-Su Ahn, Yong-Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung-Bae Park, Jung-Bum Shin, Jong-Ho Lee, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hu

ISSCC 2018 Session 12 Memory

A 16Gb LPDDR4X SDRAM with an NBTI-Tolerant

Circuit Solution, an SWD PMOS GIDL Reduction

Technique, an Adaptive Gear-Down Scheme and a Metastable-Free DQS Aligner in a 10nm Class DRAM Process Ki Chul Chun, Yong-Gyu Chu, Jin-Seok Heo, Tae-Sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Juhwan K

ISSCC 2018 Session 12 Memory

A 1.2V 64Gb 341GB/s HBM2 Stacked DRAM with Spiral Point-to-Point TSV Structure and Improved Bank Group Data Control

Jin Hee Cho, Jihwan Kim, Woo Young Lee, Dong Uk Lee, Tae Kyun Kim,

Heat Bit Park, Chunseok Jeong, Myeong-Jae Park, Seung Geun Baek, Seokwoo Choi, Byung Kuk Yoon, Young Jae Choi, Kyo Yun Lee, Daeyong Shim, Jonghoon Oh, Jinkook Kim, Seok-Hee Lee SK hynix, Gyeonggi, Korea With the recent i

ISSCC 2018 Session 12 Memory

A 16Gb/s/pin 8Gb GDDR6 DRAM with Bandwidth Extension Techniques for High-Speed Applications

Kyu-Dong Hwang, Boram Kim, Sang-Yeon Byeon, Kyu-Young Kim,

Dae-Han Kwon, Hyun-Bae Lee, Geun-Il Lee, Sang-Sic Yoon, Jin-Youp Cha, Soo-Young Jang, Seung-Hun Lee, Yong-Suk Joo, Gang-Sik Lee, Sung-Soo Xi, Soo-Bin Lim, Kyung-Ho Chu, Joo-Hwan Cho, Junhyun Chun, Jonghoon Oh, Jinkook Ki

ISSCC 2018 Session 12 Memory

A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with Improved Power Distribution and Repair Strategy

Seokbo Shim, Sungho Kim, Jooyoung Bae, Keunsik Ko, Eunryeong Lee,

Kwidong Kim, Kyeongtae Kim, Sangho Lee, Jinhoon Hyun, Insung Koh, Joonhong Park, Minjeong Kim, Sunhye Shin, Dongha Lee, Yunyoung Lee, Sangah Hyun, Wonjohn Choi, Dain Im, Dongheon Lee, Jieun Jang, Sangho Lee, Junhyun Chun

ISSCC 2018 Session 13 AI / ML

QUEST: A 7.49TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm CMOS

Kodai Ueyoshi1, Kota Ando1, Kazutoshi Hirose1,

Shinya Takamaeda-Yamazaki1, Junichiro Kadomoto2, Tomoki Miyata2, Mototsugu Hamada2, Tadahiro Kuroda2, Masato Motomura1 Hokkaido University, Sapporo, Japan Keio University, Yokohama, Japan 1 2 A key consideration for deep

ISSCC 2018 Session 13 AI / ML

UNPU: A 50.6TOPS/W Unified Deep Neural Network Accelerator with 1b-to-16b Fully-Variable Weight Bit-Precision

Jinmook Lee, Changhyeon Kim, Sanghoon Kang, Dongjoo Shin,

deep learning algorithms from face recognition to emotion recognition in mobile or embedded environments [3]. However, most works accelerate only the convolutional layers (CLs) or fully-connected layers (FCLs), and diffe

Sangyeob Kim, Hoi-Jun Yoo KAIST, Daejeon, Korea Deep neural network (D

ISSCC 2018 Session 13 AI / ML

A 9.02mW CNN-Stereo-Based Real-Time 3D Hand-Gesture Recognition Processor for Smart Mobile Devices

Sungpill Choi, Jinsu Lee, Kyuho Lee, Hoi-Jun Yoo

Recently, 3D hand-gesture recognition (HGR) has become an important feature in smart mobile devices, such as head-mounted displays (HMDs) or smartphones for AR/VR applications. A 3D HGR system in Fig. 13.4.1 enables user

KAIST, Daejeon, Korea

ISSCC 2018 Session 13 AI / ML

An Always-On 3.8μJ/86% CIFAR-10 Mixed-Signal Binary CNN Processor with All Memory on Chip in 28nm CMOS

Daniel Bankman1, Lita Yang1, Bert Moons2, Marian Verhelst2, Boris Murmann1

latency, bandwidth, and privacy has created demand for low-energy deep convolutional neural networks (CNNs). The single-layer classifier in [1] achieves sub-nJ operation, but is limited to moderate accuracy on low-comple

Stanford University, Stanford, CA; 2KU Leuven, Leuven, Belgium 1 The t

ISSCC 2018 Session 13 AI / ML

A 1.8Gb/s 70.6pJ/b 128×16 Link-Adaptive Near-Optimal Massive MIMO Detector in 28nm UTBB-FDSOI

Wei Tang1, Hemanth Prabhu2, Liang Liu2, Viktor Öwall2, Zhengya Zhang1

Lund University, Lund, Sweden data movements using holding buffers to maximize data reuse. The data reuse is especially advantageous in our design, as it requires a relatively long 28b data bit width to support a wide ra

University of Michigan, Ann Arbor, MI

ISSCC 2018 Session 13 AI / ML

A 232-to-1996KS/s Robust Compressive-Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring

Ting-Sheng Chen, Hung-Chi Kuo, An-Yeu Wu

Compressive sensing (CS) techniques enable new reduced-complexity designs for sensor nodes and help reduce overall transmission power in wireless sensor network [1-2]. Prior CS reconstruction chip designs have been descr

National Taiwan University, Taipei, Taiwan

ISSCC 2018 Session 14 Data Converters

A 50MHz-BW Continuous-Time ΔΣ ADC with Dynamic Error Correction Achieving 79.8dB SNDR and 95.2dB SFDR

Tao He1, Michael Ashburn2, Stacy Ho2, Yi Zhang1, Gabor Temes1

MediaTek, Woburn, MA 1 2 Continuous-time ΔΣ modulators (CTDSMs) are widely used in cellular handsets due to their power efficiency and inherent anti-aliasing characteristics. To achieve demanding cellular bandwidth requi

Oregon State University, Corvallis, OR

ISSCC 2018 Session 14 Data Converters

A 15.2-ENOB Continuous-Time ΔΣ ADC for a 7.3μW 200mVpp-Linear-Input-Range Neural Recording Front-End

Hariprasad Chandrakumar, Dejan Marković

Closed-loop neuromodulation with simultaneous stimulation and sensing is desired to advance deep brain stimulation (DBS) therapies. However, stimulation generates large artifacts (~100mV) at the recording sites that satu

University of California, Los Angeles, CA

ISSCC 2018 Session 14 Data Converters

A 13-ENOB 2nd-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using an Error-Feedback Structure

Shaolan Li, Bo Qiao, Miguel Gandara, Nan Sun

The noise-shaping (NS) SAR ADC is an emerging hybrid architecture that achieves high resolution and power-efficiency simultaneously by combining the merits of the SAR ADC and the ΔΣADC, making it attractive to sensor rea

University of Texas, Austin, TX

ISSCC 2018 Session 14 Data Converters

A 1.1mW 200kS/s Incremental ΔΣ ADC with a DR of 91.5dB Using Integrator Slicing for Dynamic Power Reduction

Patrick Vogelmann, Michael Haas, Maurits Ortmanns

Nyquist-rate ADCs with high resolution are needed in many applications where, for example, multiplexed operation is needed as for multichannel sensor readout. For various tasks such as averaging-based analysis or lock-in

University of Ulm, Ulm, Germany

ISSCC 2018 Session 14 Data Converters

A 280μW Dynamic-Zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW

Shoubhik Karmakar1, Burak Gönen1, Fabio Sebastiano1,

Robert Van Veldhoven2, Kofi A. A. Makinwa1 Delft University of Technology, Delft, The Netherlands NXP Semiconductors, Eindhoven, The Netherlands 1 2 Micro-power ADCs with high linearity and dynamic range (DR) are require

ISSCC 2018 Session 14 Data Converters

A 0.4V 13b 270kS/s SAR-ISDM ADC with an Opamp-Less Time-Domain Integrator

Sung-En Hsieh, Chih-Cheng Hsieh

With advanced DAC switching [1-3] and low-power comparator [4] techniques, the successive-approximation register (SAR) ADC demonstrates convincing performance with technology development for internet-of-everything (IoE)

National Tsing Hua University, Hsinchu, Taiwan

ISSCC 2018 Session 14 Data Converters

A Signal-Independent Background-Calibrating 20b 1MS/s SAR ADC with 0.3ppm INL and calibration noise (the larger μe, the faster calibration but higher calibration noise).

Hongxing Li1, Mark Maddox1, Michael C. W. Coln1, William Buckley2,

Derek Hummerston3, Naveed Naeem1 The ADC core, which implements this technique, is shown in Fig. 14.7.3. The framework is a pipelined SAR ADC architecture [3] to extend the acquisition time. The first stage has 11b resol

ISSCC 2018 Session 15 RF & Wireless

A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FOM of -246dB for IoT Applications in 65nm CMOS

Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo,

ultra-lowpower (ULP) transceivers (TRX) will be key elements in a variety of short-range network applications. The RF PLL in a TRX needs a significant amount of power due to the phase noise and spurious requirement. Comp

Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, J

ISSCC 2018 Session 15 RF & Wireless

A 23GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Saw-Tooth Chirp Modulation

Dmytro Cherniak1,2, Luigi Grimaldi2, Luca Bertulessi2, Carlo Samori2,

with high resolution require the generation of low-phase-noise, low-spurs, and highly linear chirp signals with large peak-to-peak value (chirp bandwidth) and a short period of the modulation signal [1]. In radar systems

Roberto Nonis1, Salvatore Levantino2 Infineon Technologies, Villach, A

ISSCC 2018 Session 15 RF & Wireless

A 36.3-to-38.2GHz -216dBc/Hz2 40nm CMOS Fractional-N FMCW Chirp Synthesizer PLL with a Continuous-Time Bandpass Delta-Sigma Time-to-Digital Converter rotation allows us to emulate the divider-ratio step size of 8/32 = 1/4. Since the phase rotation occurs ahead of the final divider stage, we perform only one phase shift per divider output cycle to retain the step size of 1/4 for the entire divider chain. A 2nd-order ΔΣ modulator controls the phase rotation for fractional-N division. Finally, on-chip chirp control logic modulates the PLL division ratio to generate the desired FMCW waveform profile.

Daniel Weyer1, M. Batuhan Dayanik2, Sunmin Jang1, Michael P. Flynn1

Broadcom, Irvine, CA 1 Automotive radar and other mm-wave applications require high-quality frequency synthesizers that offer fast settling and low phase noise. Analog PLLs still dominate in the mm-wave range, but all-di

University of Michigan, Ann Arbor, MI

ISSCC 2018 Session 15 RF & Wireless

A Low-Phase-Noise Digital Bang-Bang PLL with Fast Lock Over a Wide Lock Range

Luca Bertulessi, Luigi Grimaldi, Dmytro Cherniak, Carlo Samori, Salvatore Levantino

power-hungry high-resolution time/digital converters (TDCs) while demonstrating advantages in area, power consumption, and design complexity. The introduction of digital/time converters (DTCs) enables fractional-N resolu

Politecnico di Milano, Milan, Italy Digital phase-locked loops (DPLLs)

ISSCC 2018 Session 15 RF & Wireless

A Digital Frequency Synthesizer with Dither-Assisted Pulling Mitigation for Simultaneous DCO and Reference Path Coupling

Cheng-Ru Ho, Mike Shuo-Wei Chen

Injection pulling on frequency synthesizers has become a critical design challenge for high-performance wireless transceivers, especially in highly integrated multiradio platforms, imposing stringent constraints on syste

University of Southern California, Los Angeles, CA

ISSCC 2018 Session 15 RF & Wireless

A 0.01mm2 4.6-to-5.6GHz Sub-Sampling Type-I Frequency Synthesizer with –254dB FOM

Ahmad Sharkia, Shahriar Mirabbasi, Sudip Shekhar

Power consumption, Performance in terms of phase noise and integrated jitter, and Area (PPA) are three design metrics that have driven countless research efforts in CMOS frequency-synthesizer design. Design limitations a

University of British Columbia, Vancouver, Canada

ISSCC 2018 Session 15 RF & Wireless

A Dividerless Reference-Sampling RF PLL with -253.5dB Jitter FOM and <-67dBc Reference Spurs

Jahnavi Sharma, Harish Krishnaswamy

In the recent past, there have been exciting advances in dividerless PLLs, such as sub-sampling PLLs (SSPLLs) [1,2] and injection-locked clock multipliers (ILCMs) [3] that substantially reduce loop noise to cross the -25

Columbia University, New York, NY

ISSCC 2018 Session 15 AI / ML

An 82-to-108GHz -181dB-FOMT ADPLL Employing a DCO with Split-Transformer and Dual-Path SwitchedCapacitor Ladder and a Clock-Skew-Sampling DeltaSigma TDC

Zhiqiang Huang, Howard Cam Luong, HKUST, Hong Kong, China, Existing ADPLLs in [1] are limited to 60GHz and are not capab

the W-band. At 100GHz, DCOs become more sensitive to parasitics resulting in low frequency resolution. A high-resolution delta-sigma TDC is used to reduce quantization noise by noise-shaping in [2], but it suffers from l