A 16b 6GS/s Nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS

📋 论文概要

本文提出了一款16位6GS/s奈奎斯特电流舵DAC，采用16nm CMOS工艺。通过有界INL校准和温度计动态元素匹配（DEM）技术补偿电压和时序误差，实现了在高达1.9GHz频率下IMD<-90dBc的卓越线性度，同时保持低功耗和小面积。

💡 主要创新点

• 结合有界INL校准与温度计DEM，同时解决电压和时序误差，在高速下实现高线性度。
• 在16nm先进工艺下实现16位6GS/s的Nyquist DAC，面积仅0.52mm²，功耗350mW。
• 通过级联电流源、厚栅氧输出共源共栅等电路设计，提升高频性能。

🏷 关键词

📄 原文摘要

over a wide bandwidth while consuming low power and small area [1] - [6]. In this work, a 16b 6GS/s Nyquist current-steering DAC in 16nm CMOS is presented. Utilizing bounded INL calibration and thermometer DEM to tackle voltage and timing errors, this DAC achieves an INL<+/-0.25LSB, IMD<-90dBc up to 1.9GHz and SFDR>80dBc up to 900MHz while occupying an area of 0.52mm2 and dissipating 350mW from 1.0V and 3.0V supplies. Figure 22.2.1 shows a block diagram and main cell of the DAC. The DAC cell contains a cascoded current source (CS), current switches, thick-oxide output cascodes and bleeding currents. Traditionally, the current calibration was done by comparing the CS to a reference current, which yielded the best DNL. However, it is the INL that determines the linearity of the DAC, especially at low frequencies.

👥 作者与机构

Chi-Hung Lin, Koon Lun Jackie Wong, Tae-Youn Kim, Guangxi Ray Xie,

Donald Major, Greg Unruh, Sunny Raj Dommaraju, Hans Eberhart, Ardie Venes Broadcom, Irvine, CA Advanced communication systems require DACs with high linearity