A 32Gb/s 133mW PAM-4 Transceiver with DFE Based on Adaptive Clock Phase and Threshold Voltage in 65nm CMOS

📋 论文概要

本文提出一种采用65nm CMOS工艺的32Gb/s PAM-4收发器，通过基于自适应时钟相位和阈值电压的判决反馈均衡器（DFE）实现了低功耗和低误码率，在23dB信道损耗下达到BER<10^-12，功耗仅133mW。

💡 主要创新点

• 基于自适应时钟相位和阈值电压的DFE，降低了均衡器复杂度与功耗
• 采用LVDS PAM-4驱动器，在低电压下实现高效PAM-4信号输出
• 整体收发器在65nm工艺下实现32Gb/s高速率与133mW低功耗组合

🏷 关键词

📄 原文摘要

With the proliferation of the Internet of Things and mobile computing, network speed is accelerating to support data-rich services. This drives the explosion of bandwidth requirement on backplane interconnects while channel length and power efficiency remain intact. This paper presents a 32Gb/s PAM-4 transceiver fabricated in a 65nm CMOS process. It achieves a BER<10-12 through 23dB channel loss at 8GHz while consuming 133mW of power. Figure 6.7.1 shows the block diagram of the transceiver. The transmitter (TX) incorporates a low-voltage differential signaling (LVDS) PAM-4 driver in which the “Main tap” and “Post tap” work as a 4b DAC, along with a 64:8 multiplexer (MUX), 8 encoders, a clock divider and a built-in PRBS generator. The encoders generate 64b control code for different pre-emphasis strengths and signal amplitudes. Unlike the current mode logic (CML) often used in PAM-4 transmitters

👥 作者与机构

Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang, Kai Sheng, Ai He

Peking University, Beijing, China