⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种基于节拍频率量化器的全集成数字LDO，内置自适应采样机制，仅需40pF输出电容即可实现快速瞬态响应，解决了传统数字LDO响应速度慢的问题。
University of Minnesota, Minneapolis, MN Cisco Systems, San Jose, CA 1 2 Integrated voltage regulators with a wide output current/voltage dynamic range are required to support fast dynamic voltage and frequency scaling (DVFS). Low Dropout Regulators (LDOs) based on digital-intensive circuits have been gaining popularity [1]–[4] due to their compactness, process scalability, high immunity to process-voltage-temperature (PVT) variations and easy programmability for design optimization. Conventional digital LDOs utilizing a comparator and shiftregisters [1] suffer from a slow response time during a large/fast change in load current (ILOAD). Higher sampling frequency (fS) improves the response time, but at the cost of increased power consumption and reduced loop stability. Multi-bit quantizers utilizing ADCs [2-4] can reduce the settling time, however, the presence of a high resolution ADC and the control logic increases the design complexity.
Somnath Kundu1, Muqing Liu1, Richard Wong2, Shi-Jie Wen2, Chris H. Kim1