A Secure Camouflaged Logic Family Using PostManufacturing Programming with a 3.6GHz Adder Prototype in 65nm CMOS at 1V Nominal VDD Fig. 7.6.3 shows the Shmoo plots for the pre-programmed adder design under no stress (baseline), 60 seconds reverse function stress from baseline, and 60 seconds boost stress from baseline. The 60 second reverse function stress fully alters the logic function of the pre-programmed gates. The stress voltage is 3V, resulting in a current density and voltage drop per leg of 18.4mA/μm2 and 2.67V.

📋 论文概要

该论文提出了一种利用后制造编程的安全伪装逻辑系列，旨在防止IC逆向工程和IP盗窃。在65nm CMOS工艺下实现了3.6GHz的加法器原型，验证了该方法的可行性和高性能。

💡 主要创新点

• 提出后制造编程的伪装逻辑，通过动态配置电路功能来隐藏真实逻辑，抵抗逆向工程。
• 实现了3.6GHz的高速加法器原型，证明该安全技术在保持高性能方面的潜力。

🏷 关键词

📄 原文摘要

With the continued globalization of the IC manufacturing supply chain, securing that supply chain is becoming increasingly difficult and this opens the door to a myriad of security threats such as unauthorized production, counterfeiting, IP theft, and hardware Trojan Horses. A parallel and related threat is posed by advanced reverse engineering capabilities, such that even chips manufactured at the most advanced technology nodes can be de-layered, imaged, and analyzed

👥 作者与机构

Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai

Carnegie Mellon University, Pittsburgh, PA