A 23.6Mb/mm2 SRAM in 10nm FinFET Technology with Pulsed PMOS TVC and Stepped-WL for Low-Voltage Applications

📋 论文概要

本文在10nm FinFET工艺中实现了高密度低电压SRAM设计，通过脉冲PMOS TVC和阶梯字线技术降低VMIN，达到23.6Mb/mm²的面积密度，解决了FinFET技术中器件尺寸量化对紧凑6T SRAM设计的挑战。

💡 主要创新点

• 采用脉冲PMOS晶体管电压钳位（TVC）技术，有效降低SRAM阵列的低压操作门槛。
• 引入阶梯式字线（Stepped-WL）方案，优化读写稳定性，减少漏电。
• 在10nm FinFET节点实现23.6Mb/mm²的高密度SRAM，兼顾面积效率与低电压性能。

🏷 关键词

📄 原文摘要

accompanied by a sustained growth of battery-powered mobile devices, continues to drive the importance of energy and area efficient CPU and SoC designs. Low-voltage operation remains one of the primary approaches for active power reduction, but SRAM VMIN can limit the minimum operating voltage. Device size quantization continues to be a challenge for compact 6T SRAM design in FinFET technologies, where careful co-optimization of the technology and assist circuit design is required for high-density low-voltage array implementations. This paper presents two SRAM array designs in a 10nm low-power CMOS technology featuring 3rd generation FinFET transistors: a high-density 23.6Mb/mm2 array and a low-voltage 20.4Mb/mm2 array. Figure 11.1.1 shows the layout diagrams of a 0.0312μm2 high-density 6T SRAM

👥 作者与机构

Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer,

Xiaofei Wang, Eric Karl Intel, Hillsboro, OR The emergence of cloud computing and big data analytics,