⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种基于28nm工艺的32Kb嵌入式2T2MTJ STT-MRAM宏单元，通过优化读取路径和电路设计，实现了1.3ns的快速读取访问时间，解决了STT-MRAM因隧道磁阻比小导致的读取信号裕度不足和读取干扰问题，适用于需要快速可靠读取的非易失性存储应用。
nonvolatile memory (NVM) with a fast read-access time (TAC) and reliable read operations: for applications including data-logging, configurable look-up tables (LUT), eFuse, and physically unclonable functions (PUF). STT-MRAM [1-4] is a good candidate for these applications due to its fast write speed, low-voltage write, and high endurance. However, STT-MRAM suffers from a small read-signal margin (RSM) due to a small tunnel magnetoresistance ratio (TMR: (RAP-RP)/RP) between the cell resistance of parallel (P, RP) and anti-parallel (AP, RAP) states [16]. Moreover, the read-disturb behavior of STT-MRAM cells is sensitive to the BL read voltage (VBL_RD) and the stress/read time. Compact 1T1MTJ arrays are suitable for high-density applications [5-6]; however, they use a power-hungry
Tzu-Hsien Yang1,2, Kai-Xiang Li1, Yen-Ning Chiang1, Wei-Yu Lin1,
Huan-Ting Lin1, Meng-Fan Chang1 National Tsing Hua University, Hsinchu, Taiwan; 2TSMC, Hsinchu, Taiwan 1 Many IoT and wearable devices require an on-chip small-to-mid-capacity