ISSCC 2026
Session 31
Other
ALPhA-Vision: A Real-Time Always-On Vision Processor with 787μs Face Detection Latency in <5mW
Qijing Huang1, Shalini De Mello1, Brucek Khailany2 Nvidia, Santa Clara, CA, 2Nvidia, Austin, TX, 3Nvidia, Durham, NC, 4Stanford University, Stanford, CA 1 Abstract ALPhA-Vision is an always-on low-power subsystem for DNN
ISSCC 2026
Session 31
Other
LUT-SSM: A 99.3TFLOPS/W LUT-Based State-Space Model Accelerator Using Energy-Efficient Element-Wise Layer Fusion and LUT-Friendly Weight-Only Quantization
Ulsan National Institute of Science and Technology, Ulsan, Korea, 4Naver Cloud, Seongnam, Korea *Equally Credited Authors (ECAs) 1 3 Abstract State-space models (SSMs) and weight-only quantization alleviate huge external
ISSCC 2026
Session 31
Other
VARSA: A Visual Autoregressive Generation Accelerator Using Performance-Scalable Multi-Precision PE-LUT and Grid-Similarity Attention Compression
Abstract This paper presents VARSA, a 22nm visual autoregressive accelerator for efficient text-toimage generation, featuring: 1) a performance-scalable hybrid PE-LUT core; 2) multi-precision parallel processing with run
ISSCC 2026
Session 31
Other
A 51.6μJ/Token Subspace-Rotation-Based Dual-Quantized Large-Language-Model Accelerator with Fused Scale-Activation INT Datapath and Rearranged Bit-Slice LUT Computation
Abstract A 51.6μJ/token accelerator for rotation-based dual-quantized LLMs is presented. A subspace-rotation method with parallel Hadamard transposer reduces on-chip rotation power by 62.3% and area by 59.7%. A fused sca
ISSCC 2026
Session 31
Other
Revolver: Low-Bit GenAI Accelerator for Distilled-Model and CoT with Phase-Aware-Quantization and Rotation-Based Integer-Scaled Group Quantization
Abstract Revolver is a low-bit GenAI accelerator that enables reasoning and multi-turn chat on edge devices under tight memory and power budgets. It introduces Phase-Aware Precision Selection (PAPS) with Multi-Precision
ISSCC 2026
Session 31
Other
A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding
System, Hong Kong, China, 3Hefei Reliance Memory, Hefei, China, Zhejiang University, Hangzhou, China 1 4 Abstract This work presents a 55nm speculative decoding-based LLM accelerator with bumpingbased face-to-face ReRAM-
ISSCC 2026
Session 28
Other
Body-Interfaced Biosensors Wei Gao
The rise of personalized medicine is transforming healthcare through predictive and tailored strategies. I will present our progress on wearable, implantable, and ingestible biosensors for real-time molecular analysis ac
ISSCC 2026
Session 28
Other
Importance of GaN for 5G and Solid-State mm-Wave Circuits of the Future
Abstract GaN has played an important role in both RF and power devices. GaN made the rapid development and deployment of 5G base stations possible with use of its Ga-polar face. Meanwhile, the N-polar face of GaN has sho
ISSCC 2026
Session 22
Other
A 500kGy Radiation-Hardened 2.4GHz Wi-Fi Receiver for Innovative Nuclear Power Plant Decommissioning
Abstract This work presents a 2.4GHz Wi-Fi receiver in 65nm CMOS, designed with radiationhardened techniques to sustain operation under total ionizing dose to 500kGy. Such tolerance addresses the requirements of nuclear
ISSCC 2026
Session 22
Other
A Radiation-Hardened Self-Healing CMOS Imager with Online Pixel/Logic Annealing and Tile-Adaptive Compression for Space Applications
Abstract CMOS imagers in space suffer radiation-induced faults and downlink bandwidth limits. This work presents an 180nm self-healing imager with localized online thermal annealing for both pixels and logic, as well as
ISSCC 2026
Session 22
Other
A Multi-Qubit Cryo-CMOS SoC with Polar-Based Electron-Spin and PDM-Based Nuclear-Spin Controllers for Color Centers in Diamond
nitrogen-vacancy (NV) centers in diamond enables a scalable quantum platform. This work introduces a combined Class-DE RFDAC and classD PDM driver for multi-qubit electron- and nuclear-spin control. A switch allows share
ISSCC 2026
Session 22
Other
A 16-Channel Low-Power Cryo-CMOS Flux Control Pulse Generator ASIC in 14nm FinFET Technology
Daniel Ramirez2, Timothy J. Schmerbeck2, Bryce Snell2, Jeremy Ekman2, Ryan Black2, Mark Yeck1, Tom Haselhorst2, Emma Erickson2, Kevin Demsky2, Christian W. Baks1, Jonathan Kaus2, Andrea Ruffino3, Pier Andrea Francese3, A
ISSCC 2026
Session 22
Other
A Cryo-CMOS Color-Center Quantum Controller with Diamond Waveguide Micro-Chiplet Integration
Abstract We present a scalable cryo-CMOS controller for color-center-based quantum processors. A diamond waveguide micro-chiplet with NVs is pick-and-placed on CMOS with a 3D-printed prism for scalable photonic readout.
ISSCC 2026
Session 18
Other
A 28nm 47.3TFLOPs/W 894mJ/Inference Visual Autoregressive Accelerator with Differential-Amplifier Speculation and Chain-Reaction-Like Parallel Generation
*Equally Credited Authors (ECAs) Abstract To accelerate Visual Autoregressive (VAR) applications, this work implements a 28nm VAR accelerator achieving 47.3TFLOPs/W and <0.6% FID loss. A differential visual attention amp
ISSCC 2026
Session 18
Other
SMoLPU: 122.1μJ/Token Sparse MoE-Based Speculative Decoding Language Processing Unit with Adaptive-Offload NPU-CIM Core
decoding LLM processor with an NPU-CIM core. It has 3 features: 1) Token-adaptive expert refinement removes redundant expert activations and schedules expert load order, achieving 2.3×/4.2× energy efficiency improvement
ISSCC 2026
Session 18
Other
A 3.19pJ/b Electro-Optical Router with 18ns Setup Frame-Level Routing and 1-to-6 Wavelength-Flexible Link Capacity for Photonic Interposers
Vincent Josselin2, Stéphane Malhouitre2, Laurent Mendizabal2, André Myko2, Damien Saint Patrice2, Rémi Vélard2, Jean Charbonnier2 CEA-List, Grenoble, France, 2CEA-Léti, Grenoble, France 1 Abstract Global interconnect on
ISSCC 2026
Session 17
Other
Maia: A Reticle-Scale AI Accelerator
Microsoft, Mountain View, CA, 2Microsoft, Bengaluru, India 1 Abstract In Paper 17.4, the architecture and implementation of Microsoft’s MAIA AI silicon, a reticlescale 750W AI SoC, is presented. Innovation across power d
ISSCC 2026
Session 17
Other
ARIES and REGULUS: A Unified and Scalable Hardware-Software Co-Designed NPU SoC Family for On-Device and On-Premises Multimodal Inference
Y. Min, C. Song, A. Kanybek, Y. Jung, J. Song, S. Cho, H. Na, J. Park, D. Si, B. Lee, B. Park, H. Jeon Mobilint, Seoul, Korea Abstract We present a scalable NPU architecture, proven in two SoCs (ARIES and REGULUS), desig
ISSCC 2026
Session 17
Other
The STM32N6 Microcontroller: Enabling Intelligent Edge AI for IoT and Beyond
Abstract The STM32N6 microcontroller meets the growing need for intelligent edge devices in IoT, wearables, industrial automation, and smart home systems supporting real-time, energyefficient AI processing at the edge, r
ISSCC 2026
Session 17
Other
NVIDIA GB10: SoC Built for AI Acceleration
Nvidia, Westford, MA, 2Nvidia, Santa Clara, CA, 3Nvidia, Austin, TX 1 Abstract This paper details the GB10 SoC that powers the recently launched DGX™ Spark workstation. A dual-die solution, fabricated in TSMC’s 3nm proce
ISSCC 2026
Session 14
Other
Self-Programmable Twin PUFs via Photovoltaic Energy Harvesting During the Pre-Wafer-Dicing Stage
Abstract We present a CMOS self-programmable twin PUF which can be formed at the pre-waferdicing stage via photovoltaic harvesting. Two adjacent PUFs share entropy during oxide breakdown, enabling mutual authentication w
ISSCC 2026
Session 14
Other
Highly-Integrated Light-Sensing System with RF Harvesting and Transmission in Commercial N-Type IGZO Flexible Technology
Abstract A sticker-like light sensing system is demonstrated in flexible N type-only IGZO TFT. It reuses RF signals for harvested battery charging and backscattered communications, and repurposes resistors as light senso
ISSCC 2026
Session 14
Other
A 40Gb/s 8mW-OMA 1-to-N VCSEL Driver for Parallel and Wireless Optical Links Using 150nm GaN HEMT
Abstract This paper presents a 40Gb/s 1-to-N VCSEL driver using 150nm GaN HEMT with fT/fMAX of 50GHz/154GHz. The proposed topology can drive VCSEL arrays in series or parallel without the need of pre-driver, using a comm
ISSCC 2026
Session 14
Other
A Single-Chip Laser Diode Driver with Built-In Frequency-Sweep Linearization for FMCW LiDAR
Abstract A laser diode driver with supply-intrinsic current shaping for FMCW LiDAR is presented. By combining a fast optical loop and an efficient switching loop, and with the LD fitted model realized in analog circuits,
ISSCC 2026
Session 14
Other
An 8λ×38Gb/s/λ 106fJ/b Optical WDM Transmitter in 45nm CMOS SOI
Abstract This paper presents an ultra-energy-efficient MRM based 8-channel optical WDM NRZ transmitter, employing a scalable driver topology combined with monolithic electronic– photonic integration, which minimizes pack
ISSCC 2026
Session 14
Other
THz-TSI: A 0.33pJ/b 264Gb/s Through-Silicon Interconnect Module for 3D Integration Utilizing Terahertz Coupling
Abstract A through-silicon interconnect module for 3D integration utilizing THz coupling is presented, which achieves a record high data rate of 264Gb/s and efficiency of 0.33pJ/b. Both bidirectional point-to-point link
ISSCC 2026
Session 13
Other
A Nonintuitively Frequency-Staggered Wideband mm-Wave Low-Noise Amplifier
Abstract An algorithmic topology optimization framework is presented to autonomously synthesize nonintuitive, multilayered wideband mm-Wave LNAs with arbitrary stage count. Cooptimization of actives and passives directly
ISSCC 2026
Session 13
Other
An Inverse-Designed Passively Coupled N-Path Filter with gm-Boosted Active HBT Switches
Abstract A 0.8-to-2.6GHz N-path filter with gm-boosted HBT switches and inverse-designed nonresonant passive networks is presented to enhance dynamic range and tunability of passively coupled higher-order N-path filters.
ISSCC 2026
Session 13
Other
Medusa: A Quantum-Inspired 200-Variable 1016-Clause Analog k-SAT Solver
Abstract A quantum-inspired analog variable k-SAT solver supporting up to 200 variables and 1016 clauses. Enabling techniques include make/break feedback, distributed k-SAT logic, digital macro coupling, and feedback opt
ISSCC 2026
Session 13
Other
AI-Enabled End-to-End Design in RFICs with Controllable Architectural Style from ‘Classical’ to ‘Non-Intuitive’ for mm-Wave/sub-THz LNAs
*Equally Credited Authors (ECAs) 1 Abstract This paper introduces a unified algorithmic design flow for low-noise amplifiers (LNAs), spanning specifications to layout and integrating topology, architecture, circuit, and
ISSCC 2026
Session 13
Other
HYDAR: A 390K QPS, 1574K QPS/W Hybrid Analog/Digital Compute-in-RRAM Accelerator for Efficient Recommendation System
China, 4China Mobile Research Institute, Beijing, China, Xiamen Industrial Technology Research Institute, Fujian, China, 6Bytedance China, Beijing, China, 7Huawei Technologies, Shenzhen, China 1 5 Abstract We present the
ISSCC 2025
Session 33
Other
A 224GHz 19.9% TR Varactor-less VCO Utilizing a Multi-Section Switch-Loaded Coupled-Line Resonator
Analog Devices, Beaverton, OR 1 2 THz and sub-THz waves are key enablers for novel sensing and imaging solutions. THz gasphase spectroscopy, hyperspectral imaging, and high-speed communication are among many applications
ISSCC 2025
Session 33
Other
A Wideband Bidirectional Calibration-Free Frequency/Switching-Staggering 360° D-Band Phase Shifter with Frequency-Invariant Codes Achieving <2.38°/0.63dB RMS-Errors Over 24% Bandwidth
With the increasing need for high data-rate and channel throughput, the D-band (110 to 170GHz) has been actively explored for beyond-5G and 6G wireless communication, sensing, and radar applications [1,2]. To overcome th
ISSCC 2025
Session 33
Other
A 125-to-170GHz Power-Efficient Phase Shifter in SiGe BiCMOS with Outphasing Gain and Phase Corrections
Advancements in silicon technologies are opening the way to sub-THz phased-array transceivers, enabling high-resolution radar sensors, and wireless communications with a fiber-like transport capacity. Programmable phase
ISSCC 2025
Session 33
Other
A 216-to-226GHz Watt-Level GaN Solid-State Power Amplifier with Multiband Large-Signal Impedance Correction and Circuit-Package Co-Design Technique
Tianjin, China 1 2 *Equally Credited Authors (ECAs) Compact and integrated 220GHz solid-state power amplifiers (SSPAs) are important in enabling future high-data-rate wireless communication, imaging, and radar systems. S
ISSCC 2025
Session 33
Other
A 232-to-260GHz CMOS Amplifier-Multiplier Chain with a
Jinchen Wang, Daniel Sheen, Xibi Chen, Steven F. Nagle, Ruonan Han Massachusetts Institute of Technology, Cambridge, MA Terahertz (THz) signal sources and radiators are essential for a variety of future applications, suc
ISSCC 2025
Session 25
Other
A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS
Beijing, China 1 2 *Equally Credited Authors (ECAs) The growing demand for higher network bandwidth has led to a significant rise in channel density within Ethernet switches and high-performance computers. As data rates
ISSCC 2025
Session 25
Other
A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz
integrated microsystems becomes increasingly difficult as these systems scale in size and speed. These interfaces are tight pitch and parasitic sensitive, limiting the use of traditional (50Ω) test equipment. A microscal
ISSCC 2025
Session 25
Other
AI-Enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mm-Wave/sub-THz PAs between 30 and 120GHz
AI-enabled algorithmic flow for architecture discovery, circuit topology and parameter optimization for RFICs, particularly exploring design spaces beyond human intuition. RF and mmWave IC design is a complex iterative d
ISSCC 2025
Session 25
Other
A 4GS/s Fully Analog 256×256 MP-Based Cross-Correlator with 1000TOPS/W Compute Efficiency and 1.3TOPS/mm2 Compute Density in 22nm SOI CMOS
Louis, Saint Louis, MO Oregon State University, Corvallis, OR 3 University of California, San Diego, CA 4 Northeastern University, Oakland, CA 1 2 Multi-lag cross-correlations (X-Corr) are essential building blocks in ra
ISSCC 2025
Session 25
Other
A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100% Solvability and 31.7μs Solution Time
Zhengya Zhang, Michael P. Flynn University of Michigan, Ann Arbor, MI *Equally Credited Authors (ECAs) The Boolean satisfiability (SAT) problem is a fundamental NP-complete problem, and efficiently solving it would revol
ISSCC 2025
Session 23
Other
Slim-Llama: A 4.69mW Large-Language-Model Processor with Binary/Ternary Weights for Billion-Parameter Llama Model
Recently, multiple ASICs [1-6] have been proposed to accelerate large language models (LLMs). However, the enormous number of LLM parameters leads to significant energy consumption due to external memory access (EMA). Wh
ISSCC 2025
Session 23
Other
An 88.36TOPS/W Bit-Level-Weight-Compressed Large-Language-Model Accelerator with Cluster-Aligned INT-FP-GEMM and Bi-Dimensional Workflow Reformulation
range of natural language processing (NLP) tasks, becoming an essential part of modern society [1-4]. This exceptional performance can be attributed to huge model size and autoregressive computation [5,6]. However, these
ISSCC 2025
Session 23
Other
BROCA: A 52.4-to-559.2mW Mobile Social Agent System-on-Chip with Adaptive Bit-Truncate Unit and Acoustic-Cluster Bit Grouping computation. The ACE PE processes input data in a bit-serial manner, where four 8b weights are accumulated in parallel, leading to a decrease in compute energy proportional to the input bitwidth. As a result, an average reduction of 4.4b in input bitwidth and a 4.7× speedup can be achieved, reducing computation energy by 44.5% at the RG.
Dongseok Im, Sangyeob Kim, Sangjin Kim, Taekwon Lee, Hoi-Jun Yoo Figure 23.7.4 illustrates the proposed ACBU, which achieves runtime bitwidth reduction of the vocoder input feature map to reduce computation energy in the
ISSCC 2025
Session 23
Other
MEGA.mini: A Universal Generative AI Processor with a New Big/Little Core Architecture for NPU
Chung-Ang University, Seoul, Korea 1 2 The global AI market is growing explosively with the rise of generative AI applications, such as image manipulation and text-to-text/image/video creation. AI was primarily expected
ISSCC 2025
Session 23
Other
MAE: A 3nm 0.168mm2 576MAC Mini AutoEncoder with Line-based Depth-First Scheduling for Generative AI in Vision on Edge Devices
Chia-Yuan Cheng, Hung-Wei Chih, Po-Han Chiang, Ming-Hsuan Chiang, Yuan-Jung Kuo, Yu-Wei Wu, Yi-Syuan Chen, Po-Heng Chen, Sandy Huang, Ming-En Shih, Chia-Ping Chen, Abrams Chen, ShenKai Chang, Chih-Ming Wang, Po-Yu Yeh, J
ISSCC 2025
Session 23
Other
Nebula: A 28nm 109.8TOPS/W 3D PNN Accelerator Featuring
Changchun Zhou1, Tianling Huang1, Yanzhe Ma1, Yuzhe Fu1, Xiangjie Song1, Siyuan Qiu1, Jiacong Sun1, Min Liu1, Ge Li1, Yifan He2, Yuchao Yang1,3, Hailong Jiao1 Peking University, Shenzhen, China Reconova Technologies, Xia
ISSCC 2025
Session 23
Other
EdgeDiff: 418.4mJ/Inference Multi-Modal Few-Step Diffusion Model Accelerator with Mixed-Precision and Reordered Group Quantization
need for high-performing image-generative models, including the diffusion model (DM) [2, 3]. A conventional DM requires numerous UNet-based denoising timesteps (~50), leading to high computation and external memory acces
ISSCC 2025
Session 23
Other
HuMoniX: A 57.3fps 12.8TFLOPS/W Text-to-Motion Processor with Inter-Iteration Output Sparsity and Inter-Frame Joint Similarity
media applications, such as film production and AR/VR. This process involves creating human joint movements and constructing detailed 3D meshes, like human skin, for each joint (see Fig. 23.10.1). It used to require hour
ISSCC 2025
Session 13
Other
A Via-Programmable DNN-Processor Fabrication Toward 1/40th Mask Cost
Growing interest in healthcare has led to the development of many wearable battery-powered artificial-intelligence internet-of-things (AI-IoT) devices for continuous monitoring a wide variety of vital signs [1, 2] (Fig.
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