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ISSCC 2025Session 25 · HIGH-CONCEPTS AT HIGH FREQUENCIESOther28nm CMOS

A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS

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📋 论文概要

本文提出了一种集成通道分析仪,用于高速高密度信号完整性测量,覆盖DC至40GHz频率范围,功耗仅为99.5mW/端口。该设计解决了传统矢量网络分析仪(VNA)在功耗、尺寸和成本方面的不足,适用于以太网交换机和高性能计算机中的通道缺陷检测。

💡 主要创新点

核心指标
99.5mW/端口功耗,DC-40GHz频率范围
工艺节点
28nm CMOS
重要性
发表年份
ISSCC 2025

🏷 关键词

信号完整性通道分析仪矢量网络分析仪低功耗28nm CMOS

📄 原文摘要

Beijing, China 1 2 *Equally Credited Authors (ECAs) The growing demand for higher network bandwidth has led to a significant rise in channel density within Ethernet switches and high-performance computers. As data rates continue to climb, electrical links, such as printed circuit board (PCB) traces and coaxial cables, suffer from greater defects including reflection, crosstalk, and insertion loss. Therefore, low-power and highly efficient signal integrity (SI) measurements are crucial for detecting defects in communication equipment. Traditionally, vector network analyzers (VNAs) and sampling oscilloscopes with time-domain reflectometer modules are employed for SI measurement. However, these instruments are power-hungry, expensive, and inefficient

👥 作者与机构

Guangdong Wu*1, Yuanliang Li*1, Bingyi Ye*1,2, Fangzhu Li1, Xin Liu1, Haowei Niu1,

Ruixu Wang1, Dunshan Yu1, Weixin Gai1,3 Peking University, Beijing, China East China Normal University, Shanghai, China 3 Beijing Advanced Innovation Center for Integrated Circuits,

分类:Other · 年份:ISSCC 2025