A Via-Programmable DNN-Processor Fabrication Toward 1/40th Mask Cost

📋 论文概要

该论文提出了一种基于通孔可编程神经元阵列（VPNA）的单掩模可定制制造方案，用于低功耗DNN处理器，旨在解决传统ASIC掩模成本高昂的问题，将掩模成本降低至1/40。

💡 主要创新点

• 提出通孔可编程神经元阵列（VPNA），通过单一掩模定制实现多种DNN架构，大幅降低制造成本。
• 采用单掩模定制化制造方案，适用于可穿戴AI-IoT设备，兼顾低功耗与灵活性。

🏷 关键词

📄 原文摘要

Growing interest in healthcare has led to the development of many wearable battery-powered artificial-intelligence internet-of-things (AI-IoT) devices for continuous monitoring a wide variety of vital signs [1, 2] (Fig. 13.6.1). While analog-based compute-in-memory (CiM) ASICs are effective in reducing power consumption, it is not realistic to prepare a wide variety of ASICs each of which incurs substantial mask costs. To address this issue, a single-mask customizable fabrication scheme for low-power DNN processors utilizing via-programmable neuron array (VPNA) is proposed. While diverse DNN layers are realized by arranging the placement of vias on a uniquely designed base chip, there are two major challenges: the large area overhead of the programmable routing wires and the large number of nodes and parameters required to implement DNN layers. The bit- and neuron-serial circuit (BNSC) technique reduces the implementation area by

👥 作者与机构

Jaewon Shin, Rei Sumikawa, Dongzhu Li, Mototsugu Hamada, Atsutake Kosuge

University of Tokyo, Tokyo, Japan