ARIES and REGULUS: A Unified and Scalable Hardware-Software Co-Designed NPU SoC Family for On-Device and On-Premises Multimodal Inference

📋 论文概要

本文提出了一种统一且可扩展的NPU架构，并在两个SoC（ARIES和REGULUS）中实现，旨在高效执行从视觉到大语言模型的多样化AI工作负载。通过硬件-软件协同设计，采用边界和分布感知的混合精度量化方案，在保持模型精度的同时高效处理复杂激活函数，并支持跨核心、集群和芯片的无缝扩展。

💡 主要创新点

• 提出统一可扩展的NPU架构，支持跨核心、集群和芯片的线性缩放，并配备统一的编程模型，简化部署。
• 采用边界和分布感知的混合精度量化方案，在硬件-软件协同设计下平衡模型精度与推理效率。

🏷 关键词

📄 原文摘要

Y. Min, C. Song, A. Kanybek, Y. Jung, J. Song, S. Cho, H. Na, J. Park, D. Si, B. Lee, B. Park, H. Jeon Mobilint, Seoul, Korea Abstract We present a scalable NPU architecture, proven in two SoCs (ARIES and REGULUS), designed to efficiently execute diverse AI workloads from vision to large language models. The architecture scales seamlessly across cores, clusters, and chips via a unified programming model. Our holistic hardware–software co-design preserves model accuracy through a bound- and distribution-aware mixed-precision quantization scheme, while efficiently handling complex activation functions via a non-uniform piecewise-linear method. Silicon measurements demonstrate near-linear performance scaling and high power and bandwidth efficiency on both vision and language workloads. The shift of intelligent compute to edge devices requires neural processing units (NPUs) to efficiently execute a wide spectrum of workloads—from compute-bound convolutional

👥 作者与机构

D. Shin, H. Yang, S. Jeon, J. Park, S. Han, J. Park, J. Lee, J. Kim, H. Kim, Y. Oh, M. Kim, C. Jung, W. Kim, S. Kim, H. Jeong, G. Kim, K. Lee, G. Song,