A 4GS/s Fully Analog 256×256 MP-Based Cross-Correlator with 1000TOPS/W Compute Efficiency and 1.3TOPS/mm2 Compute Density in 22nm SOI CMOS

📋 论文概要

该论文提出了一种全模拟的256×256多延迟互相关器，采用基于存储处理（MP）的架构，在4GS/s采样率下实现了1000TOPS/W的计算效率和1.3TOPS/mm²的计算密度，解决了传统数字互相关器能效低、功耗高的问题。

💡 主要创新点

• 提出全模拟MP架构，将延迟和互相关操作直接在模拟域完成，避免了高速ADC和数字MAC的功耗瓶颈。
• 采用256×256大规模并行处理单元，实现了4GS/s的高吞吐率和极高的能效比。

🏷 关键词

📄 原文摘要

Louis, Saint Louis, MO Oregon State University, Corvallis, OR 3 University of California, San Diego, CA 4 Northeastern University, Oakland, CA 1 2 Multi-lag cross-correlations (X-Corr) are essential building blocks in radar and communication for range/velocity detection and synchronization [1,2]. Performing X-corrs necessitates efficient delay and correlation blocks. Traditionally, high bandwidth X-corr is performed using high-speed ADCs followed by digital multiply-and-accumulates (MACs). However, 5–20 TOPS/W X-Corr efficiencies lead to 0.1–1W per cross-correlator [1,2], limiting deployability in power-constrained applications. Alternatively, to realize X-corr using prior single-lag analog correlators [3,4], wideband analog delays (>10ns delays with 4GHz BW) should be integrated on chip to enable multiple lags. Furthermore, replicating N analog

👥 作者与机构

Aswin Undavalli1, Kareem Rashed2, Gert Cauwenberghs3, Shantanu Chakrabartty1,

Arun Natarajan2, Aravind Nagulu1,4 Washington University in St