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该论文提出了一种采用自适应阈值ADC的64Gb/s PAM-4收发器，通过非均匀量化和LMS算法优化阈值，降低了ADC功耗并改善了链路误码率。
for PAM-4 links above 50Gb/s [1,2], although fewer bits are sufficient and offer lower power for short reach (SR) channels. To further reduce the power consumption of ADC-based wireline transceivers, non-uniform quantization has been explored [3,4] using performance metrics for the complete link, such as bit-error rate (BER), to optimize the quantizer thresholds. Both [3,4] are PAM-2 (NRZ) receivers, demonstrating non-uniform quantization specifically for a decision feedback equalizer (DFE) at 10Gb/s and a feedforward equalizer (FFE) at 4Gb/s respectively. An LMS algorithm in [4] adjusts the threshold levels requiring fine-tuning (8b resolution). This paper presents a 64Gb/s PAM-4 transceiver utilizing an ADCbased receiver (RX), with an analog front-end (AFE) based on a 6b, 1b folding,
Luke Wang1, Yingying Fu2, MarcAndre LaCroix3, Euhan Chong3, Anthony Chan Carusone1
University of Toronto, Toronto, Canada Huawei, Markham, Canada 3 Huawei, Ottawa, Canada 1 2 ADC-based transceivers having up to 8 bits of resolution have been reported