A Dividerless Reference-Sampling RF PLL with -253.5dB Jitter FOM and <-67dBc Reference Spurs

📋 论文概要

该论文提出了一种无分频器的参考采样RF PLL，通过创新的参考采样技术打破了传统PLL中抖动FOM与参考杂散之间的权衡，实现了-253.5dB的抖动FOM和低于-67dBc的参考杂散。

💡 主要创新点

• 提出参考采样架构，无需分频器，从根本上降低了环路噪声。
• 通过优化采样机制和环路带宽，同时实现了极低的抖动和参考杂散，突破了传统PLL的性能瓶颈。

🏷 关键词

📄 原文摘要

In the recent past, there have been exciting advances in dividerless PLLs, such as sub-sampling PLLs (SSPLLs) [1,2] and injection-locked clock multipliers (ILCMs) [3] that substantially reduce loop noise to cross the -250dB jitter-power figure-of-merit (FOMj) barrier. However, there exists a fundamental trade-off between FOMj and reference spurs in PLLs, although the mechanisms vary across architectures. Narrow PLL bandwidths are necessary for reducing spurs through filtering, but this can conflict with the optimal bandwidth for jitter. In SSPLLs, buffers, isolating the VCO from the sub-sampled phase detector (SSPD) (Fig. 15.7.1), reduce spurs at the expense of noise and power consumption. Smaller sample capacitances in the SSPD reduce spurs generated by mismatch-induced charge sharing, charge injection, and tank frequency modulation at the expense of increased kT/C noise. Consequently, the SSPLL of [2] achieves spur <-80dBc

👥 作者与机构

Jahnavi Sharma, Harish Krishnaswamy

Columbia University, New York, NY