⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一款16Gb LPDDR4X SDRAM，采用10nm级DRAM工艺，通过NBTI容忍电路、SWD PMOS GIDL降低技术、自适应降速方案和无亚稳态DQS对齐器，解决了NBTI退化、漏电和时序对齐等可靠性问题。
Technique, an Adaptive Gear-Down Scheme and a Metastable-Free DQS Aligner in a 10nm Class DRAM Process Ki Chul Chun, Yong-Gyu Chu, Jin-Seok Heo, Tae-Sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Juhwan Kim, Hyunchul Yoon, Chang-Ho Shin, Sanguhn Cha, Hyung-Jin Kim, Young-Sik Kim, Kyungryun Kim, Young-Ju Kim, Wonjun Choi, Dae-Sik Yim, Inkyu Moon, Young-Ju Kim, Junha Lee, Young Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, Woongdae Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong-Jin Cho, Hoon Shin, Hangyun Jung, Sanghyuk Kwon, Kyuchang Kang, Jongmyung Lee, Yujung Song, Young-Jae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, Seok-Hun Hyun, Seungbum Ko, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang Samsung Electronics, Hwaseong, Korea High-density and high-speed DRAM requirements have been ever-increasing to achieve a better user experience for mobile systems, by adopting QHD
Circuit Solution, an SWD PMOS GIDL Reduction