A 0.02mm2 Fully Synthesizable Period-Jitter Sensor Using Stochastic TDC Without Reference Clock and Calibration in 10nm CMOS Technology

📋 论文概要

提出了一种全可综合的周期抖动传感器（PJS），无需模拟电路、参考时钟或校准，通过改进随机时间数字转换器（TDC）实现。解决了片上时钟质量评估依赖低噪声模拟电路和额外校准的问题。

💡 主要创新点

• 首次实现完全可综合的周期抖动传感器，无需任何模拟电路。
• 无需参考时钟和校准，采用随机TDC实现抖动测量。
• 面积仅0.02mm²，适合大规模SoC集成。

🏷 关键词

📄 原文摘要

becomes challenging. To effectively manage the tight jitter performance required by an SoC, the clock quality should be directly evaluated at every point where the clock is used in the SoC. In previous work [1-3], on-chip clock measurements were carried out, but these circuits are difficult to integrate into varied systems due to their special requirements of low-noise analog circuitry, a clean reference clock and additional calibration. We propose a fully synthesizable period jitter sensor (PJS), requiring no analog circuit, reference or calibration by improving upon a stochastic time-to-digital converter (TDC) [4]. The inverter delay chain of the stochastic TDC in [4] has a weakness: it may lose delayed signals due to its lengthy delay chain. It is replaced with a short-pulse delay chain, which does not

👥 作者与机构

Kangyeop Choo, Hyunik Kim, Wooseok Kim, Jihyun Kim, Taeik Kim, Hyungjong Ko

Samsung Electronics, Hwaseong, Korea With the increasing clock speed and complexity of SoCs, measuring clock jitter