A 65nm 1Mb Nonvolatile Computing-in-Memory ReRAM Macro with Sub-16ns Multiply-andAccumulate for Binary DNN AI Edge Processors

📋 论文概要

该论文提出了一种基于65nm工艺的1Mb非易失性存内计算ReRAM宏单元，用于二进制深度神经网络（DNN）的边缘AI设备。通过亚16ns的乘累加操作，解决了传统冯·诺依曼架构中数据搬运的能耗和延迟瓶颈，实现了低功耗、高速的神经网络推理。

💡 主要创新点

• 首次在65nm工艺下实现1Mb规模的ReRAM存内计算宏单元，支持二进制DNN的乘累加操作。
• 实现了亚16ns的乘累加延迟，显著提升了边缘AI设备的推理速度。
• 利用非易失性ReRAM存储权重，降低了静态功耗并支持快速唤醒，适合边缘设备应用。

🏷 关键词

📄 原文摘要

Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang, Tzu-Hsiang Hsu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang National Tsing Hua University, Hsinchu, Taiwan Many artificial intelligence (AI) edge devices use nonvolatile memory (NVM) to store the weights for the neural network (trained off-line on an AI server), and require lowenergy and fast I/O accesses. The deep neural networks (DNN) used by AI processors [1,2] commonly require p-layers of a convolutional neural network (CNN) and q-layers of a fully-connected network (FCN). Current DNN processors that use a conventional (von-Neumann) memory structure are limited by high access latencies, I/O energy consumption, and hardware costs. Large working data sets result in heavy accesses across the memory hierarchy, moreover large amounts of intermediate data are also generated due to the large number of multiply-and-accumulate (MAC) operations for

👥 作者与机构

Wei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li,