A Combined All-Digital PLL-Buck Slack Regulation System with Autonomous CCM/DCM Transition Control and 82% Average Voltage-Margin Reduction in a 0.6-to-1.0V Cortex-M0 Processor

📋 论文概要

该论文提出了一种结合全数字锁相环（PLL）和Buck转换器的松弛调节系统，用于集成电路的集成电压调节（IVR）。该系统实现了自主的连续导通模式（CCM）与断续导通模式（DCM）转换控制，以应对宽负载电流范围下的效率优化问题，平均效率达到82%。

💡 主要创新点

• 首次将全数字PLL与Buck转换器结合，实现松弛调节架构，优化瞬态响应和电压跌落裕量。
• 提出自主CCM/DCM转换控制机制，无需外部干预即可根据负载电流自动切换工作模式，提升轻载效率。

🏷 关键词

📄 原文摘要

Naveen John, Visvesh S. Sathe University of Washington, Seattle, WA Integrated Voltage Regulation (IVR) using buck converters enables efficient, finegrained supply-voltage control in modern SoC domains [1]. However, existing IVR implementations face several challenges. As voltage domains continue to shrink, reduced per-domain decoupling capacitance requires rapid IVR transient response, leading to unfavorable efficiency and supply droop margin trade-offs. Additionally, digital domains exhibit a wide load current (Iload) range, requiring capabilities for autonomous transition between Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). All-digital IVR solutions are particularly desirable for ease of integration in SoCs. Several techniques have been proposed to address these IVR challenges. Autonomous CCM-DCM transition is proposed in [2], but requires analog comparators and does not account for bridge driver delays for zero current switching,

👥 作者与机构

Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li,