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本文介绍了采用28nm FDSOI CMOS工艺的16至64Gb/s PAM-4极短距离收发器，实现了4.9pJ/b的能效，解决了PAM-4调制下低功耗收发器设计中的高线性度与宽带宽挑战。
Hongyang Zhang2, Walter Audoglio1, Oscar Belotti1, Augusto Andrea Rossi1, Guido Albasini1, Massimo Pozzoni1, Simone Erba1, Andrea Mazzanti2 STMicroelectronics, Pavia, Italy University of Pavia, Pavia, Italy 1 2 PAM-4 modulation paired with forward error correction schemes has been introduced in recent wireline communication standards operating up to 56Gb/s per-lane. PAM-4 enables a more efficient use of the available link bandwidth but, compared to NRZ, design of low-power transceivers entails new challenges. Transmitters must deliver high swing with wide bandwidth and high linearity [13]. The multilevel signal suffers from heightened sensitivity to channel loss and reflections, because transitions between adjacent levels are impaired from ISI generated by 3× larger pk-to-pk transitions [4]. As a result, enhanced equalization accuracy is mandatory before symbol detection. ADC-based receivers benefit from powerful equalization and detection in the digital
Emanuele Depaoli1, Enrico Monaco1, Giovanni Steffan1, Marco Mazzini1,