A Flash Memory Controller for 15μs Ultra-Low-Latency SSD Using High-Speed 3D NAND Flash with 3μs Read Time

📋 论文概要

本文提出了一种闪存控制器，结合高速3D NAND闪存（读取时间3μs），实现了15μs超低延迟的SSD，解决了传统闪存延迟约50μs的问题，缩小了与DRAM的差距。

💡 主要创新点

• 通过优化控制器架构和协议设计，将SSD延迟降低至15μs，接近新型非易失性存储器水平。
• 采用读取时间仅3μs的高速3D NAND闪存，作为延迟优化的基础。
• 在系统层面实现控制器与闪存的协同优化，支持超低延迟数据访问。

🏷 关键词

📄 原文摘要

Daehyun Kim, Chulseung Lee, Youra Choi, Shine Kim, Dongku Kang, Geunyeong Yu, Jaehong Kim, Jaechun Park, Ki-Whan Song, Ki-Tae Park, Sangyeun Cho, Hwaseok Oh, Daniel DG Lee, Jin-Hyeok Choi, Jaeheon Jeong Samsung Electronics, Hwaseong, Korea In a memory hierarchy, there are various classes of memory systems depending on the access latency. A typical memory hierarchy consists of a CPU cache, DRAM, and an SSD or HDD. The DRAM has an access latency of 100ns, while flash memory has a latency of about 50μs [1]. Recently, new non-volatile memories with latencies of less than 10μs, including PRAM, MRAM, and ReRAM

👥 作者与机构

Wooseong Cheong, Chanho Yoon, Seonghoon Woo, Kyuwook Han,