An Always-On 3.8μJ/86% CIFAR-10 Mixed-Signal Binary CNN Processor with All Memory on Chip in 28nm CMOS

📋 论文概要

提出一款混合信号二进制CNN处理器，在28nm CMOS工艺上实现全片上存储，以3.8μJ/图能耗达到CIFAR-10数据集86%准确率，解决边缘端低功耗高精度图像分类问题。

💡 主要创新点

• 采用混合信号二进制计算单元，通过二进制权重和激活值大幅降低计算能耗和存储需求
• 实现近内存计算架构，所有权重和特征图存储于片上SRAM，避免片外DRAM访问能耗
• 集成完整CIFAR-10分类网络，在低功耗下同时兼顾了中等复杂任务的精度需求

🏷 关键词

📄 原文摘要

latency, bandwidth, and privacy has created demand for low-energy deep convolutional neural networks (CNNs). The single-layer classifier in [1] achieves sub-nJ operation, but is limited to moderate accuracy on low-complexity tasks (90% on MNIST). Larger CNN chips provide dataflow computing for high-complexity tasks (AlexNet) at mJ energy [2], but edge deployment remains a challenge due to offchip DRAM access energy. This paper describes a mixed-signal binary CNN processor that performs image classification of moderate complexity (86% on CIFAR-10) and employs near-memory computing to achieve a classification energy of 3.8μJ, a 40× improvement over TrueNorth [3]. We accomplish this using (1) the BinaryNet algorithm for CNNs with weights and activations constrained to

👥 作者与机构

Daniel Bankman1, Lita Yang1, Bert Moons2, Marian Verhelst2, Boris Murmann1

Stanford University, Stanford, CA; 2KU Leuven, Leuven, Belgium 1 The trend of pushing deep learning from cloud to edge due to concerns of