⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种适用于0.3V至1.2V宽电压范围的频率可缩放分数N全数字锁相环（ADPLL），通过一种推测性双参考插值时间数字转换器（TDC）解决了传统模拟PLL在低电压下难以工作的问题，实现了宽频率锁定范围和低功耗。
Power management with dynamic frequency control has been a key feature in battery-operated systems. It effectively reduces energy consumption by the microcontroller in mobile systems towards meeting ultra-low-power constraints for implantable system-on-a-chip wireless nodes by optimal profiling of voltage and frequency according to the operating modes and tasks. The essential circuit block for such applications is the phase-locked loop (PLL), supporting a wide frequency lock range scaled along with the supply voltage [1, 2]. Traditional design approaches of analog PLLs, however, are not suited for wide supply voltage operation since they suffer from degraded accuracy when subject to a reduction in supply headroom. On the other hand, all-digital PLL implementations
Minseob Lee1, Shinwoong Kim2, Hwasuk Cho1, Jahyun Koo1,
Kwang-Hee Choi2, Jin-Hyeok Choi2, Byungsub Kim1, Hong-June Park1, Jae-Yoon Sim1 Pohang University of Science and Technology, Pohang, Korea Samsung Electronics, Hwaseong, Korea 1