A Low-Phase-Noise Digital Bang-Bang PLL with Fast Lock Over a Wide Lock Range

📋 论文概要

该论文提出了一种低相位噪声的数字Bang-Bang锁相环，通过引入数字时间转换器（DTC）实现分数-N分辨率，并解决了Bang-Bang鉴相器过载导致的锁定失败或瞬态过长问题，实现了快速锁定和宽锁定范围。

💡 主要创新点

• 采用数字时间转换器（DTC）实现高光谱纯度的分数-N分辨率，降低量化噪声。
• 设计了一种机制避免Bang-Bang鉴相器过载，确保在宽频率步进下快速锁定。

🏷 关键词

📄 原文摘要

power-hungry high-resolution time/digital converters (TDCs) while demonstrating advantages in area, power consumption, and design complexity. The introduction of digital/time converters (DTCs) enables fractional-N resolution at high spectral purity [1]. The design of a bang-bang digital PLL for wireless standards has two main challenges: quantization noise must be kept below the tolerable spot phase noise and fast lock must be guaranteed even for wide frequency steps. However, the overload of the BPD causes bang-bang PLLs to fail lock or to exhibit extremely long transients. A similar issue appears in the design of sub-sampling PLLs. This problem is exacerbated when the bang-bang PLL is designed for low phase noise for the tight resolution required of the digitally controlled oscillator (DCO). Fast

👥 作者与机构

Luca Bertulessi, Luigi Grimaldi, Dmytro Cherniak, Carlo Samori, Salvatore Levantino

Politecnico di Milano, Milan, Italy Digital phase-locked loops (DPLLs) based on binary phase detectors (BPDs) avoid