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ISSCC 2018Session 14 · HIGH-RESOLUTION ADCsData Converters

A Signal-Independent Background-Calibrating 20b 1MS/s SAR ADC with 0.3ppm INL and calibration noise (the larger μe, the faster calibration but higher calibration noise).

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📋 论文概要

该论文提出了一种信号无关的背景校准技术,实现了20位分辨率、1MS/s采样率的流水线SAR ADC,INL达到0.3ppm。通过流水线架构延长采集时间,并采用残差放大器自动归零和mini-ADC解析前4位MSB,解决了高精度ADC的校准噪声问题。

💡 主要创新点

核心指标
20b 1MS/s, 0.3ppm INL
重要性
发表年份
ISSCC 2018

🏷 关键词

背景校准SAR ADC高精度低INL流水线架构

📄 原文摘要

Derek Hummerston3, Naveed Naeem1 The ADC core, which implements this technique, is shown in Fig. 14.7.3. The framework is a pipelined SAR ADC architecture [3] to extend the acquisition time. The first stage has 11b resolution and the CDAC1 structure is similar to Fig. 14.7.2. The value of Cfb is chosen to provide a residue gain of 32. A mini-ADC is included to resolve the first 4 MSBs. Once the first 4 MSBs are decided, the SAR logic loads them to CDAC1, and continues with the remaining bit trials in the first stage while switch S1 is opened and the residue amplifier (RA) is in auto-zero mode. After all CDAC1 bits are decided, switch S1 is closed to connect CDAC1 with RA, and generate the first residue voltage, which is sampled by ADC2a. Following the ADC2a sampling, CDAC1 is re-configured and ADC2b is connected to RA sampling the second residue voltage. Shortly after this, ADC2a and ADC2b

👥 作者与机构

Hongxing Li1, Mark Maddox1, Michael C. W. Coln1, William Buckley2,

分类:Data Converters · 年份:ISSCC 2018