A Fractional-N Digital PLL with Background-DitherNoise-Cancellation Loop Achieving <-62.5dBc WorstCase Near-Carrier Fractional Spurs in 65nm CMOS

📋 论文概要

本文提出了一种分数N数字锁相环，通过背景抖噪消除环路来抑制由时间数字转换器或增量累加调制器量化误差引起的分数N杂散。实验结果表明，该设计实现了最差情况下近载波分数杂散优于-62.5 dBc，有效改善了确定性抖动和互调产物。

💡 主要创新点

• 提出了一种背景抖噪消除环路，能够在锁相环正常工作期间持续抑制分数杂散，无需校准或中断操作。
• 采用数字域补偿技术，对量化误差进行实时抵消，从而降低近载波杂散水平。

🏷 关键词

📄 原文摘要

Fractional-N digital phase-locked loops (DPLLs) are highly reconfigurable, scalable, and useful for synthesizing clocks with fine frequency resolution for modem RF, mixed-signal and digital VLSI systems. One critical design challenge is the associated fractional-N spurs, which result from the quantization error of the time-to-digital converter (TDC) or delta-sigma modulator when using multimodulus fractional dividers. Those unwanted spurs can cause degraded deterministic jitter, reciprocal mixing, and undesired spectrum emissions, depending on the actual PLL application. Various techniques have been used to mitigate fractional spurs. One is to apply dithering [1–3] in the input reference path to randomize the periodic phase error pattern, hence reducing spur magnitude. However, the dithering signal also increases the phase noise floor. A two-level dithering scheme [3] has been adopted to limit noise degradation (but

👥 作者与机构

Cheng-Ru Ho, Mike Shuo-Wei Chen

University of Southern California, Los Angeles, CA