A 1.17pJ/b 25Gb/s/pin Ground-Referenced SingleEnded Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator

📋 论文概要

本文提出了一种在16nm CMOS工艺下实现的接地参考单端串行链路，以1.17pJ/b的能效和25Gb/s/pin的数据速率支持片外和片内封装通信。该设计旨在利用低成本有机封装和传统PCB，满足多芯片系统中对高带宽、低功耗互连的需求。

💡 主要创新点

• 采用接地参考单端信号传输，相比差分信号降低功耗和引脚数，同时保持高速性能。
• 在16nm CMOS中实现25Gb/s/pin的数据速率，能效仅1.17pJ/b，适用于片上和片外封装通信。

🏷 关键词

📄 原文摘要

Xi Chen2, Sudhir S. Kudva2, Sanquan Song2, Stephen G. Tell1, Nikola Nedovic2, Wenxu Zhao1a, Sunil R. Sudhakaran2, C. Thomas Gray1, William J. Dally2 Nvidia, Durham, NC; 2Nvidia, Santa Clara, CA 1 a now with Broadcom, Irvine, CA Toward the end of the Moore’s-law era, increases in system complexity will rely more heavily on packaging technology. Systems will increasingly comprise multiple chips that must be linked by high-speed data channels carrying a substantial fraction of on-chip bandwidth. To take advantage of inexpensive organic packages and conventional printed circuit (PC) boards, data links that are both energy and pin efficient are needed. A link between neighboring packages is by far the more challenging application due to increased cross-talk, signal attenuation, and reflections from impedance discontinuities. The combination of signal integrity challenges and production margining requires increased

👥 作者与机构

John M. Wilson1, Walker J. Turner1, John W. Poulton1, Brian Zimmer2,