A 2.5µW 0.0067mm2 Automatic Back-Biasing Compensation Unit Achieving 50% Leakage Reduction in FDSOI 28nm over 0.35-to-1V VDD Range

📋 论文概要

该论文提出了一种自动背偏置补偿单元，在FDSOI 28nm工艺下实现了50%的漏电降低，覆盖0.35V至1V的电压范围，解决了传统最坏情况设计和后硅调谐带来的功耗过高问题。

💡 主要创新点

• 提出了一种自动背偏置补偿单元，无需外部控制即可动态调节体偏置以补偿工艺、温度、老化及电压变化。
• 在0.35V至1V的宽电压范围内实现了50%的漏电降低，且面积仅为0.0067mm²，功耗仅2.5µW。

🏷 关键词

📄 原文摘要

STMicroelectronics, Crolles, France 1 2 Worst-case design and post-silicon tuning are well established digital design practices reducing timing violations in presence of process, temperature, aging and voltage variations, but they suffer from extra power consumption due to overdesign [1]. Adaptive voltage scaling (AVS) [2] and body bias modulation [1] are well-known strategies to dynamically ensure that the digital core can operate at a targeted frequency, even in the presence of delay degradation due to variations. In a multiple voltage islands context, AVS requires many integrated supply generators, such as switched capacitor converters that need to be controlled accurately. Also, for fine-grained compensation, level shifters are required, impacting circuit performance. As FDSOI technology offers the ability to adjust transistor speed through high sensitivity (85mV/VBB) VTH tuning by acting

👥 作者与机构

Anthony Quelen1, Gael Pillonnet1, Philippe Flatresse2, Edith Beigné1

CEA-LETI-MINATEC, Grenoble, France,