A 65nm 4Kb Algorithm-Dependent Computing-inMemory SRAM Unit-Macro with 2.3ns and 55.8TOPS/W Fully Parallel Product-Sum Operation for Binary DNN Edge Processors

📋 论文概要

本文提出一种基于65nm工艺的4Kb算法依赖的计算存储SRAM单元宏，实现了全并行乘积和运算，解决了深度神经网络中卷积和全连接层的计算瓶颈，同时降低功耗和硬件成本，适用于边缘AI设备。

💡 主要创新点

• 提出算法依赖的计算内存（Algorithm-Dependent Computing-in-Memory）架构，将乘积和运算融入SRAM阵列中，减少数据搬移功耗。
• 实现全并行乘积和操作，达到2.3ns的运算延迟和55.8TOPS/W的高能效比，显著提升推理速度与能效。
• 针对二元神经网络优化，在保持高精度的同时降低计算和存储开销，缓解内存墙问题。

🏷 关键词

📄 原文摘要

Technology of China, Sichuan, China 4 Arizona State University, Tempe, AZ 1 3 For deep-neural-network (DNN) processors [1-4], the product-sum (PS) operation predominates the computational workload for both convolution (CNVL) and fullyconnect (FCNL) neural-network (NN) layers. This hinders the adoption of DNN processors to on the edge artificial-intelligence (AI) devices, which require low-power, low-cost and fast inference. Binary DNNs [5-6] are used to reduce computation and hardware costs for AI edge devices; however, a memory bottleneck still remains. In Fig. 31.5.1 conventional PE arrays exploit parallelized computation, but suffer from inefficient single-row SRAM access to weights and intermediate data. Computing-inmemory (CIM) improves efficiency by enabling parallel computing, reducing memory

👥 作者与机构

Win-San Khwa1,2, Jia-Jing Chen1, Jia-Fang Li1, Xin Si3, En-Yu Yang1,

Xiaoyu Sun4, Rui Liu4, Pai-Yu Chen4, Qiang Li3, Shimeng Yu4, Meng-Fan Chang1 National Tsing Hua University, Hsinchu, Taiwan; 2TSMC, Hsinchu, Taiwan University of Electronic Science and