A 0.4V 13b 270kS/s SAR-ISDM ADC with an Opamp-Less Time-Domain Integrator

📋 论文概要

该论文提出了一种工作在0.4V超低电压下的13位270kS/s SAR-ISDM混合模数转换器，通过采用无运放时域积分器解决了传统SAR ADC在高分辨率下受限于DAC失配和比较器噪声的问题，实现了高能效和高精度转换。

💡 主要创新点

• 提出了一种无运放的时域积分器，用于实现sigma-delta调制中的噪声整形，避免了传统运放带来的功耗和面积开销。
• 将SAR ADC与增量型sigma-delta调制器（ISDM）结合，通过混合架构在低电压下实现13位分辨率，同时保持低功耗。

🏷 关键词

📄 原文摘要

With advanced DAC switching [1-3] and low-power comparator [4] techniques, the successive-approximation register (SAR) ADC demonstrates convincing performance with technology development for internet-of-everything (IoE) applications. However, the power efficiency and accuracy of SAR ADCs over 12b are limited by DAC mismatch and comparator noise requirements, which increases by 4× for each additional 1b of resolution. Hybrid-SAR ADCs using sigma-delta modulators (SDMs) for fine conversion have been reported to reduce noise using oversampling and noise shaping operations with a power penalty from the required operational amplifier (opamp) for integrator realization. An integrator using a passive summing technique was reported [5] without using an opamp, however, the resulting gain loss degraded the effective resolution. This work presents a SAR-ISDM ADC with an opamp-less time-domain integrator

👥 作者与机构

Sung-En Hsieh, Chih-Cheng Hsieh

National Tsing Hua University, Hsinchu, Taiwan