A 5GHz 7nm L1 Cache Memory Compiler for High-Speed Computing and Mobile Applications

📋 论文概要

本文提出一种适用于7nm工艺的L1缓存内存编译器，支持5GHz操作频率，旨在满足高速计算和移动应用的需求。该方法通过编译器生成的缓存宏替代传统全定制设计，在保持高性能的同时改善密度和可扩展性。

💡 主要创新点

• 采用内存编译器自动生成L1缓存宏，替代全定制设计，降低设计复杂度并提升灵活性。
• 在7nm节点实现5GHz操作频率，兼顾高速与低功耗，适用于高性能计算和移动场景。
• 可能采用新型电路技术（如优化的读路径或位单元）平衡速度与密度。

🏷 关键词

📄 原文摘要

will typically determine the maximum frequency (fMAX) of the processor core. Companies that mass produce high-performance microprocessors commonly have the L1 cache consist of fully-custom macros: to ensure that the performance of the L1 cache does not limit the fMAX or throughput of the processor. In addition, it is also common for the custom L1 cache designs to use a two-port 8T or a large 6T bitcell, along with domino read logic and very short BL [2,3]. These designs tradeoff density and area for high performance. This paper presents a different approach, one which can satisfy a range of different applications; a memory compiler that can generate more than 10,000 different high-speed L1 cache macro configurations is proposed. The 7nm L1-cache compiler described in this paper

👥 作者与机构

Michael Clinton1, Rajinder Singh1, Marty Tsai1, Shayan Zhang1,

Bryan Sheffield1, Jonathan Chang2 TSMC, Austin, TX TSMC, Hsinchu, Taiwan 1 2 In high performance computing (HPC) applications, the speed of the L1 cache