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该论文提出了一种面积高效的PWM残余混叠减少技术，实现了低静态电流（0.96mA）和低失真（THD+N 0.0032%）的1.45W D类音频放大器，解决了闭环D类放大器中因PWM高频残余混叠导致的相位误差和占空比误差失真问题。
Low quiescent current (IQ) is critical for Class-D audio amplifiers in mobile devices to extend battery usage time [1], since typical audio signals have a high crest factor of 10 to 20dB. In addition, low distortion is also important for audio fidelity. Distortion sources in closed-loop Class-D amplifiers can be classified into two types. One is attributed to the nonlinearities of PWM modulators and power stages, while the other is due to the aliasing of fed-back PWM high-frequency residuals, the latter of which comprises phase-error and duty-cycle-error distortions [2]. Figure 3.6.1 shows 2nd-order closed-loop amplifiers and existing techniques for enhancing an amplifier’s linearity. Increasing the loop filter order to obtain a higher in-band loop gain by using more integrators [3] or the singleamplifier-biquad [4] suppresses all aforementioned distortions except for the phase-error distortion, which can be suppressed by adding a phase-error-free
Shih-Hsiung Chien, Yi-Wen Chen, Tai-Haur Kuo
National Cheng Kung University, Tainan, Taiwan