A 5GHz 370fsrms 6.5mW Clock Multiplier Using a Crystal-Oscillator Frequency Quadrupler in 65nm CMOS

📋 论文概要

本文提出了一种基于晶振频率四倍频的5GHz时钟乘法器，通过提高振荡器噪声抑制带宽来改善相位噪声，在65nm CMOS工艺中实现了370fsrms抖动和6.5mW功耗。解决了传统基于环形振荡器的时钟乘法器因参考频率限制导致噪声抑制带宽不足的问题。

💡 主要创新点

• 提出使用晶体振荡器频率四倍频产生低噪声参考，突破了传统PLL/MDLL/ILCM中参考频率对噪声抑制带宽的限制。
• 实现了高带宽噪声抑制，在5GHz输出下仅消耗6.5mW功耗，同时获得370fsrms的低抖动性能。

🏷 关键词

📄 原文摘要

(RO-based) clock multipliers is typically limited by oscillator noise. The most power-efficient method for improving the phase noise of such clock multipliers is by increasing the oscillator noise suppression bandwidth (FBW). While FBW depends on the type of clock multiplier, the maximum achievable FBW is limited by the reference frequency (FREF). For instance, in phase-locked loops (PLLs) FBW = FREF/10, while multiplying delay-locked loops (MDLLs) [1] and injection-locked clock multipliers (ILCMs)

👥 作者与机构

Karim M. Megawer, Ahmed Elkholy, Daniel Coombs, Mostafa G. Ahmed,

Ahmed Elmallah, Pavan Kumar Hanumolu University of Illinois, Urbana, IL Phase noise performance of ring-oscillator-based