⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种128×16大规模MIMO检测器，采用链路自适应近最优算法，在28nm UTBB-FDSOI工艺上实现了1.8Gb/s的数据速率和70.6pJ/b的能效。通过压缩阵列架构和最大化数据重用的保持缓冲器，解决了传统检测器面积大、功耗高的问题。
Lund University, Lund, Sweden data movements using holding buffers to maximize data reuse. The data reuse is especially advantageous in our design, as it requires a relatively long 28b data bit width to support a wide range of channel conditions. The condensed array architecture reduces silicon area by 62% compared to the regular systolic array. Moreover, the condensed array shortens data movement delay and dedicates a larger fraction of a clock period to data processing. 1 2 This work presents a 2.0mm2 128×16 massive MIMO detector IC that provides 21dB array gain and 16× multiplexing gain at the system level. The detector implements iterative expectation-propagation detection (EPD) for up to 256-QAM modulation. Tested with measured channel data [1], the detector achieves 4.3dB processing gain over state-of-the-art massive MIMO detectors [2, 3], enabling 2.7× reduction in transmit power for battery-powered mobile terminals. The IC
Wei Tang1, Hemanth Prabhu2, Liang Liu2, Viktor Öwall2, Zhengya Zhang1
University of Michigan, Ann Arbor, MI