An 82-to-108GHz -181dB-FOMT ADPLL Employing a DCO with Split-Transformer and Dual-Path SwitchedCapacitor Ladder and a Clock-Skew-Sampling DeltaSigma TDC

📋 论文概要

该论文提出了一种82-108GHz的ADPLL，采用分裂变压器和双路径开关电容梯级的DCO，实现了-181dB的FOMT。解决了W波段DCO因寄生效应导致的频率分辨率低和调谐范围有限的问题。

💡 主要创新点

• 提出分裂变压器（split-transformer）结构，实现高Q值的可变电感，替代低Q的变容管进行精细调谐。
• 采用双路径开关电容梯级（dual-path switched-capacitor ladder），在保持高Q值的同时扩大调谐范围。

🏷 关键词

📄 原文摘要

the W-band. At 100GHz, DCOs become more sensitive to parasitics resulting in low frequency resolution. A high-resolution delta-sigma TDC is used to reduce quantization noise by noise-shaping in [2], but it suffers from large noise from its ring-oscillator. Moreover, the frequency tuning range of existing W-band VCOs is limited to only ~11% because using switched capacitors and varactors with low Q (<3) is not useful. To achieve fine tuning without varactors for high Q (>8), a variable inductor, implemented with a transformer and a variable resistor, is used in [3,4]. However, the variable resistor significantly degrades the Q with a minimum value Qmin limited to Qmin≈2/k2≈2/TR, where k is the transformer coupling coefficient and TR is the tuning range. Employing a split transformer with variable resistors for wide tuning range, dual-path exponentially scaled switched-capacitor (SC) ladders for high frequency resolution, and a clock-skewsampling delta-sigma TDC for low close-in phase no

👥 作者与机构

Zhiqiang Huang, Howard Cam Luong, HKUST, Hong Kong, China, Existing ADPLLs in [1] are limited to 60GHz and are not capable of operating in