A 7.4-to-14GHz PLL with 54fsrms Jitter in 16nm FinFET for Integrated RF-Data-Converter SoCs

📋 论文概要

该论文提出了一款工作在7.4-14GHz频率范围的PLL，实现了54fsrms的极低抖动，采用16nm FinFET工艺，用于集成射频-数据转换器SoC。解决了直接射频数据转换器对低相位噪声和低杂散采样时钟的需求，以最小化自混频和邻道混频。

💡 主要创新点

• 实现了7.4-14GHz的宽频带覆盖，同时保持54fsrms的超低抖动，满足高性能射频数据转换器需求。
• 采用16nm FinFET工艺设计，结合先进的PLL架构和电路技术，在宽频带内实现优异的相位噪声性能。

🏷 关键词

📄 原文摘要

Ying Cao1, Shaojun Ma1, Christophe Erdmann2, Brendan Farley2, Yohan Frans1, Ken Chang1 Xilinx, San Jose, CA; 2Xilinx, Dublin, Ireland 1 Direct-RF data converters [1,2] have seen increased adoption in remote-radiohead TX and RX, due to their unparalleled bandwidth and flexibility. However, since these converters need to directly synthesize and sample multi-GHz radio signals, the sampling clock must exhibit excellent phase-noise performance, to minimize self- and adjacent- channel mixing, and strong suppression of reference and harmonic spurs, to meet stringent out-of-band emissions and minimize aliased energy. Furthermore, a wide range of sampling frequencies is required for the flexibility to cover multiple bands. Due to these stringent requirements, typically, external PLLs are employed, adding to the BOM cost. This work presents techniques for a fully integrated 7.4-to-14GHz PLL in 16nm FinFET that has 54fsrms

👥 作者与机构

Didem Turker1, Ade Bekele1, Parag Upadhyaya1, Bob Verbruggen2,