A -242dB FOM and -75dBc-Reference-Spur Ring-DCO-Based All-Digital PLL Using a Fast Phase-Error Correction Technique and a Low-Power Optimal-Threshold TDC

📋 论文概要

本文提出一种基于环形DCO的全数字锁相环，采用快速相位误差校正(FPEC)技术，通过模拟注入锁定时钟乘法器的相位重新对齐机制实现超低抖动，同时利用积分器特性降低参考杂散并支持高倍频因子。

💡 主要创新点

• 提出FPEC技术，在数字域模拟ILCM的相位重新对齐，实现与ILCM相当的超低抖动。
• 通过引入积分器，克服了ILCM参考杂散大和倍频因子受限的问题，实现了-75dBc参考杂散和高倍频因子。

🏷 关键词

📄 原文摘要

To improve efficiency in the use of silicon, there have been many efforts to develop ring-oscillator-based clock generators with low jitter. A PLL using a fast phaseerror correction (FPEC) technique [1] is one promising architecture. By emulating the phase-realignment mechanism of an injection-locked clock multiplier (ILCM), the FPEC PLL can achieve ultra-low jitter that is almost comparable to that of ILCMs. In addition, since the FPEC PLL has an integrator in its transfer function, it can also achieve a low reference spur and a high multiplication factor (N), which is different from ILCMs. However, the FPEC PLL of an analog implementation in

👥 作者与机构

Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi

Ulsan National Institute of Science and Technology, Ulsan, Korea