← 返回论文列表 📄 下载原文 PDF  ISSCC 2018 · 2.3
ISSCC 2018Session 2 · PROCESSORSDigital Processors14nm Tri-Gate CMOS

An Energy-Efficient Graphics Processor Featuring

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

该论文提出了一款采用细粒度动态电压频率调整(DVFS)与集成电压调节器的节能图形处理器,通过执行单元Turbo和保持性睡眠模式在14nm三栅极CMOS工艺中实现能效提升。解决了传统图形处理器在动态功耗管理和能效优化方面的挑战。

💡 主要创新点

工艺节点
14nm Tri-Gate CMOS
重要性
发表年份
ISSCC 2018

🏷 关键词

图形处理器动态电压频率调整集成电压调节器执行单元Turbo保持性睡眠14nm三栅极CMOS

📄 原文摘要

Execution-Unit Turbo, and Retentive Sleep in 14nm Tri-Gate CMOS Pascal Meinerzhagen1, Carlos Tokunaga1, Andres Malavasi1, Vaibhav Vaidya1, Ashwin Mendon1, Deepak Mathaikutty1, Jaydeep Kulkarni1, Charles Augustine1, Minki Cho1, Stephen Kim1, George Matthew1, Rinkle Jain1, Joseph Ryan1, Chung-Ching Peng1, Somnath Paul1, Sriram Vangal1, Brando Perez Esparza1, Luis Cuellar1, Michael Woodman1, Bala Iyer1, Subramaniam Maiyuran2, Gautham Chinya1, Chris Zou1, Yuyun Liao1, Krishnan Ravichandran1, Hong Wang1, Muhammad Khellah1, James Tschanz1, Vivek De1 Intel, Hillsboro, OR; 2Intel, Folsom, CA 1 Graphics workloads are highly dynamic in nature, using multi-threaded SIMD execution units (EUs), fixed-function units, samplers, and media accelerators to provide ever-increasing amounts of graphics performance. These workloads are often limited by power and thermal constraints, requiring dynamic voltage/frequency

👥 作者与机构

Fine-Grain DVFS with Integrated Voltage Regulators,

分类:Digital Processors · 年份:ISSCC 2018