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本文提出了一种采用分割CDAC系数乘法器的低功耗3.25GS/s 4阶可编程模拟FIR滤波器，用于宽带模拟信号处理。该设计利用离散时间电路技术克服深亚微米CMOS中的模拟设计挑战，实现了高采样率与可编程性。
Discrete-time (DT) circuits provide a means to overcome the analog-circuit design challenges in deeply scaled digital CMOS technologies while benefitting from the reduced switch on-resistance and parasitic capacitance, resulting in lower dynamic power dissipation. In addition, such DT analog circuits can reduce the requirements on analog-to-digital converters that precede digital processing [1]. Recent DT domain filters achieve high-order narrowband programmable filtering with low power and high linearity even under low supply voltage [2,3]. However, DT switched capacitor circuits have not been considered for wideband analog signal processing (ASP) applications such as on-chip implementation of FIRbased beamforming [4,5]. While the AFIR filter proposed in [6] is a suitable approach for programmable wideband ASP applications, in that design only symmetric and positive coefficient sets were possible and measured performance
Shinwoong Park1, Dongseok Shin2, Kwang-Jin Koh1, Sanjay Raman1
Virginia Tech, Blacksburg, VA; 2Intel, Hillsboro, OR