A 0.45V Sub-mW All-Digital PLL in 16nm FinFET for Bluetooth Low-Energy (BLE) Modulation and Instantaneous Channel Hopping Using 32.768kHz Reference

📋 论文概要

该论文提出了一种在16nm FinFET工艺中实现的0.45V亚毫瓦全数字PLL，用于蓝牙低功耗（BLE）调制和瞬时信道跳频。通过降低DCO的闪烁相位噪声，允许在接收数据包期间冻结调谐字更新并直接FM调制DCO，从而在低功耗下实现快速信道获取和相位噪声抑制。

💡 主要创新点

• 采用0.45V超低电压供电，实现亚毫瓦级功耗的全数字PLL架构。
• 通过降低DCO闪烁相位噪声，在接收数据包期间冻结调谐字更新并直接FM调制DCO，简化了调制路径并降低了功耗。
• 在16nm FinFET工艺中实现了BLE调制和瞬时信道跳频功能，兼顾了低功耗与快速信道切换性能。

🏷 关键词

📄 原文摘要

short-range wireless transceivers, such as BLE, is to use a crystal oscillator (XO) in the tens-of-MHz range as a frequency reference (FREF) to phase lock an RF oscillator [1-4]. This ensures a sufficiently wide PLL bandwidth of tens to hundreds of kHz to quickly acquire a new channel and to suppress lower-frequency phase noise (PN) of the RF oscillator. The latter requirement can be alleviated by substantially lowering the flicker PN of a digitally controlled oscillator (DCO) thus allowing to freeze its tuning word updates during receive (RX) packets and further directly FM-modulating the DCO during transmit (TX) packets [1]. However, an all-digital PLL (ADPLL) is still needed just to quickly settle the DCO to each new channel.

👥 作者与机构

Min-Shueh Yuan1, Chao-Chieh Li1, Chia-Chun Liao1, Yu-Tso Lin1,

Chih-Hsien Chang1, Robert Bogdan Staszewski2 TSMC, Hsinchu, Taiwan; 2University College Dublin, Dublin 4, Ireland 1 The current paradigm of frequency synthesis for