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该论文设计了一种在14nm CMOS工艺下实现的112Gb/s PAM-4源串联终端(SST)发射机，采用8抽头前馈均衡(FFE)以补偿信道损耗，实现了2.6pJ/b的高能效。这项工作解决了高速PAM-4发射机在均衡能力和功耗之间的权衡问题。
Thomas Morf1, Alessandro Cevrero1, Marcel Kossel1, Lukas Kull1, Danny Luu1,2, Ilter Ozkaya1,3, Thomas Toifl1 IBM Zurich Research Laboratory, Rueschlikon, Switzerland 2 ETH Zurich, Zurich, Switzerland 3 EPFL, Lausanne, Switzerland 1 The ongoing demand for higher data rates in wireline and optical communications has led to emerging standards in the 100Gb/s+ regime [1]. Although these standards are still in the definition phase they will rely on multi-level signaling such as PAM-4 along with an increasing amount of digital signal processing. In the foreseeable future, a high-performance TX will consist of a CMOS DSP frontend followed by a high sampling rate data converter [2,3], whose design remains a significant challenge. This paper presents a 112Gb/s PAM-4 SST TX that is based on a quarter-rate 56GS/s 8b SST DAC along with a digital 8-tap FIR filter for channel equalization. A block diagram of the TX is shown in Fig. 6.2.1. The TX consists of a 56GS/s 8b
Christian Menolfi1, Matthias Braendli1, Pier Andrea Francese1,